Patents by Inventor Chi-Kai Liu

Chi-Kai Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194765
    Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.
    Type: Application
    Filed: January 29, 2024
    Publication date: June 13, 2024
    Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
  • Patent number: 11923432
    Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
  • Publication number: 20130339576
    Abstract: A method for constructing an address mapping table of a solid state drive is provided. The address mapping table is stored in a non-volatile memory of the solid state drive. The method includes the following steps. After the solid state drive is powered on, a command from a host is received. Then, a logical allocation address is calculated according to a logical block address corresponding to the command. Then, the calculated logical allocation address is defined as an initial address, and a specified number of logical allocation addresses starting from the initial address and corresponding physical allocation addresses are loaded into a cache memory, so that a first portion of the address mapping table is constructed into the cache memory. Afterwards, the solid state drive responds the command according to the first portion of the address mapping table.
    Type: Application
    Filed: October 25, 2012
    Publication date: December 19, 2013
    Applicant: LITE-ON IT CORPORATION
    Inventors: Chi-Kai Liu, Yen-Heng Chen