Abstract: An integrated circuit device comprising an improved bonding pad structure. The device has a semiconductor substrate. A plurality of active MOS devices are formed on the semiconductor substrate. The device has an interlayer dielectric layer overlying the plurality of active MOS devices and at least one single metal bonding pad formed on the interlayer dielectric layer and directly over at least one of the active devices. At least four edge regions are formed on a square shape of the at least one single metal bonding pad. An angled cut region is formed on each of the four edge regions. The device has a buffer metal layer free region located between the plurality of active MOS devices and the at least one single metal bonding pad. The buffer metal layer free region does not have a buffer metal layer in the interlayer dielectric layer.

Abstract: An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

Abstract: An e-fuse and an e-fuse control circuit are provided. The e-fuse includes a polysilicon layer and a metal silicide layer stacked on the polysilicon layer. The e-fuse operates in an open state when the silicide layer is broken by burning while one portion of the polysilicon layer is exposed.

Abstract: A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

Abstract: An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: A portable control apparatus includes a driver, a baseband controller, and a crystal oscillator. The driver includes an oscillating circuit that generates a feedback signal. The baseband controller coupled to the driver receives the feedback signal, and outputs a calibrating signal to the driver according to the feedback signal. The crystal oscillator coupled to the baseband controller generates an accurate output frequency for operating the baseband controller.

Abstract: A capacitive touch screen sensing apparatus is provided. The apparatus includes a protecting layer; a sensing layer under the protecting layer for sensing a touch to generate a position signal; and a DC common voltage signal layer electrically connected with a DC voltage for shielding against signal interferences.

Abstract: An integrated circuit device comprising an improved bonding pad structure. The device has a semiconductor substrate. A plurality of active MOS devices are formed on the semiconductor substrate. The device has an interlayer dielectric layer overlying the plurality of active MOS devices and at least one single metal bonding pad formed on the interlayer dielectric layer and directly over at least one of the active devices. At least four edge regions are formed on a square shape of the at least one single metal bonding pad. An angled cut region is formed on each of the four edge regions. Preferably, the angled cut region is within a periphery of the square shape of the at least one single metal bonding pad. A passivation layer having an opening is formed over the at least single metal bonding pad. The device has a buffer metal layer free region between the plurality of active MOS devices and the at least one single metal bonding pad.

Abstract: A touch screen includes an LCD panel; a display controller for processing a video signal to generate a panel control signal and a sensing control signal, with the panel control signal controlling the LCD panel so that the LCD panel displays images according to the panel control signal; a touch panel, for generating the sensing signal in response to a touch; and a sensing circuit, coupled to the touch panel and the display controller, for receiving the sensing signal and the sensing control signal to generate a position signal with reference to the sensing control signal.

Abstract: A driving circuit on a liquid crystal display (LCD) panel and associated control method is provided. The LCD panel connected to a display control circuit via a flexible print circuit (FPC) includes a master source driver, for outputting a digital image signal in compliance with a first electrical specification via an FPC board and converting the digital image signal to a gate driving signal and a slave source driving signal, which are in compliance with a second electrical specification; a gate driver, for receiving the gate driving signal in compliance with the second electrical specification; and a slave source driver, for receiving the slave source driving signal in compliance with the second electrical specification. The master source driver, the slave source driver and the gate driver drive a thin-film transistor (TFT) on the LCD panel.

Abstract: An e-fuse and an e-fuse control circuit are provided. The e-fuse includes a polysilicon layer and a metal silicide layer stacked on the polysilicon layer. The e-fuse operates in an open state when the silicide layer is broken by burning while one portion of the polysilicon layer is exposed.

Abstract: A touch sensing device capable of accurately detecting a touched position on a touch panel includes a touch panel, a conversion unit and a calculation unit. The touch panel having a plurality of horizontal sensing lines and vertical sensing lines generates a plurality of horizontal sensing signals and vertical sensing signals in response to a touch on the touch panel. The conversion unit generates a plurality of two-dimensional (2D) sensing signals according to the horizontal and vertical sensing signals. The calculation unit determines a touched position on the touch panel according to the 2D sensing signals.

Abstract: A charge pump circuit includes a first voltage supply circuit configured to provide a first supply voltage in response to a first and second input signals. A first capacitor is coupled to the first voltage supply circuit. A first switch circuit is configured to provide a second supply voltage to a second terminal of the first capacitor in response to a first control signal. A second switch circuit is coupled to the second terminal of the first capacitor. A second capacitor is coupled to the second switch circuit. The second switch circuit is configured to cause charge transfer from the first capacitor to the second capacitor in response to a second control signal. The charge pump also includes an output terminal coupled to the second capacitor to provide an output voltage, the output voltage being higher than the first supply voltage, the output voltage being also higher than the second supply voltage.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD regions are disposed between the N+ implant regions, and pocket implants underlie each of the NLDD regions. Current discharge paths are defined by corresponding NLDD regions and pocket implants when a voltage of the first node exceeds a breakdown voltage. In a specific embodiment, the breakdown voltage is less than a breakdown voltage for a logic gate oxide.

Abstract: A new processing sequence is provided for the process of creating salicided layers of CoSix. A conventional gate electrode is formed up to the point where the process of salicidation has to be performed. At that time a layer of cobalt is deposited over the surface of the gate electrode, a first anneal is applied to the deposited layer of cobalt. The layer of cobalt is then selectively etched to formed the contact surfaces of the gate electrode after which, significantly and as a major deviation from previous methods of creating a salicided layer of CoSix, silicon is implanted into the surface of the created layer of CoSix. This silicon implant relieves a silicon deficiency into the first annealed layer of CoSix, this silicon deficiency has experimentally been determined as being the essential cause for the occurrence of Co—Si agglomeration after a second thermal anneal. After the silicon implantation has been completed, a second thermal anneal is applied to the created layer of CoSix.

Abstract: A method is taught for removing a silicon oxynitride ARC from over a polysilicon gate after the gate is patterned. The ARC is removed by wet etching without damaging or undercutting the polysilicon gate. This is accomplished by protecting the lateral sides of a polysilicon gate with a thin silicon oxide layer prior to the performing the wet etch. The method is primarily directed towards removal of a silicon oxynitride ARC layer from the upper surface of the polysilicon gate electrode in a salicide process, although a silicon nitride layer may also be removed by the same method. The protective silicon oxide is formed by rapid thermal oxidation in O2 or by plasma oxidation in O2 and H2O. After oxidation, the ARC is removed with hot H3PO4. The protective silicon oxide protects the lateral surfaces of the polysilicon gate from attack by the acid. Following implantation of LDD regions, a conformal sidewall layer is deposited and the sidewalls formed in the conventional manner.

Abstract: A method of forming a misalignment immune antifuse is presented comprised of the following steps. A partially processed semiconductor wafer is provided, containing at least one device electrically connected to a conducting region extending almost to the wafer surface, where the conducting region is surrounded by a dielectric layer which reaches the wafer surface. A blanket layer of amorphous silicon is deposited followed by deposition of a thin blanket layer of TiN and these layers are etched down to the dielectric surface except for that above the conducting region and some of the surrounding dielectric. A thin native oxide is formed over the exposed surface of the amorphous silicon. This is followed by deposition of a thicker TIN layer and of a metallization layer, which are patterned and etched so that contact is made to the lower layers. The oxidation step is repeated so as to oxidize any amorphous silicon surface that may have been inadvertently exposed in the last etching step.