Patents by Inventor Chi Keung Lee

Chi Keung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10531937
    Abstract: A new dental implant system with positive abutment screw locking and retrieval mechanisms is provided. The abutment screw is positively locked by a keying pin to improve fatigue life. The abutment screw is also equipped with a special feature that greatly improves the retrievability of the broken screw from inside the implant. In addition, the keying pin is designed with a lock nut as a sub-assembly for ease of installation.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 14, 2020
    Inventors: Chi Keung Lee, Gurpreet Singh Narula
  • Patent number: 10234893
    Abstract: A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: March 19, 2019
    Assignee: Nvidia Corporation
    Inventors: Guillermo J Rozas, Jason Golbus, Chi Keung Lee
  • Publication number: 20180368951
    Abstract: A new dental implant system with positive abutment screw locking and retrieval mechanisms is provided. The abutment screw is positively locked by a keying pin to improve fatigue life. The abutment screw is also equipped with a special feature that greatly improves the retrievability of the broken screw from inside the implant. In addition, the keying pin is designed with a lock nut as a sub-assembly for ease of installation.
    Type: Application
    Filed: October 25, 2017
    Publication date: December 27, 2018
    Inventors: Chi Keung LEE, Gurpreet Singh NARULA
  • Publication number: 20160174394
    Abstract: An optical communications module having an improved latching/delatching mechanism is provided. The slider arms of the latching/delatching mechanism are partially encased in the module housing. Partially encasing the slider arms in the module housing provides the latching/delatching mechanism with greater rigidity and eliminates the possibility of the latching/delatching mechanism becoming dislodged from the module housing due to excessive force being applied to the bail of the latching/delatching mechanism. In addition, the slider arms do not come into contact with the cage as the module housing is being inserted into and extracted from the cage. Distal portions of the slider arms remain outside of the module housing to allow hook features of the distal portions to disengage the cage latches during the delatching process.
    Type: Application
    Filed: March 31, 2014
    Publication date: June 16, 2016
    Inventor: Chi Keung Lee
  • Patent number: 9298868
    Abstract: A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 29, 2016
    Assignee: NVIDIA Corporation
    Inventors: Vikas Agrawal, Shrivathsa Bhargavravichandran, Binh Pham, Jay Chen, Sridhar Krishnamurthy, Umang Shah, Chi Keung Lee
  • Publication number: 20150340128
    Abstract: A zipper sleeve is provided that is made entirely or almost entirely of highly flame-retardant meta-aramid material to provide the zipper sleeve with highly flame-retardant characteristics. The zipper teeth rows of the zipper mechanism are attached directly to respective side edges of opposite sides of a sheet of highly flame-retardant material that will be used to make the sleeve. By attaching the zipper teeth rows directly to the meta-aramid material, the process of attaching the teeth can be fully automated, which ensures that the teeth will be precisely aligned. This feature allows a highly flame-retardant zipper sleeve made entirely or almost entirely out of meta-aramid material to be manufactured at relatively low costs and with very high yield.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventor: Chi Keung Lee
  • Publication number: 20150331210
    Abstract: An AOC system includes an AOC optical module, a substantially cylindrical cable jacket, a bundle of optical fibers in the cable jacket, a metallic fiber holder, and a spring clip. A portion of the metallic fiber holder is seated within a recess in a metallic AOC module housing. The spring clip resiliently biases the portion of the metal fiber holder seated within the housing recess into contact with the metallic housing, promoting EMI shielding.
    Type: Application
    Filed: December 30, 2013
    Publication date: November 19, 2015
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Chi Keung Lee
  • Patent number: 8949652
    Abstract: In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: February 3, 2015
    Assignee: Nvidia Corporation
    Inventor: Chi Keung Lee
  • Publication number: 20150028106
    Abstract: A method of manufacturing a smart card (20) embedded with an integrated circuit module (28) and an antenna coil (8) includes step (a), embedding an antenna coil (8) on a core sheet (6), (b), laminating the core sheet (6) with a number of outer sheets (10, 12, 14, 16) to form a laminated panel (18), (c), forming a cavity (22) in the laminated panel (18) to expose two ends (24) of the antenna coil (8), and (d), connecting two electric contact regions (30) of an integrated circuit module (28). The exposed ends (24) of the antenna coil (8) are connected by a mezzanine electrode diffusion welding method, controlled by a transformer output manipulation energy output control method.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 29, 2015
    Inventor: Chi Keung LEE
  • Publication number: 20140380257
    Abstract: A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Vikas AGRAWAL, Shrivathsa BHARGAVRAVICHANDRAN, Binh PHAM, Jay CHEN, Sridhar KRISHNAMURTHY, Umang SHAH, Chi Keung LEE
  • Publication number: 20140355934
    Abstract: An optics system for use with a parallel optical communications module is provided that includes a support structure for supporting the ends of the optical fibers in a way that ensures that the ends of the optical fibers are maintained in precise optical alignment with respective optical coupling elements of the optics system. The support structure makes it virtually impossible for there to be any misalignment between the ends of the optical fibers and the respective optical coupling elements of the optics system to prevent misalignment problems from occurring. In addition, the optics system is configured in such a way that the likelihood that the ends of the optical fibers will be damaged as they are inserted into the optics system is very small.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventors: Bing Shao, Ye Chen, Chi Keung Lee, Andrew J. Schmit
  • Publication number: 20140337659
    Abstract: A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.
    Type: Application
    Filed: May 13, 2013
    Publication date: November 13, 2014
    Applicant: Nvidia Corporation
    Inventors: Guillermo J. Rozas, Jason Golbus, Chi Keung Lee
  • Publication number: 20130133181
    Abstract: A parallel optical communications module is equipped with an EMI waveguide (WG) device having a tube-like structure that surrounds portions of one or more optical fiber ribbon cables that pass through the tube-like structure and connect to the module. The EMI WG device attenuates EMI to acceptable levels to provide the module with effective EMI shielding capability.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: AVAGO TECHNOLOGIES FIBER IP (SINGAPORE) PTE. LTD.
    Inventor: Chi Keung Lee
  • Publication number: 20130117598
    Abstract: In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Applicant: NVIDIA CORPORATION
    Inventor: Chi Keung Lee
  • Patent number: D690373
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: September 24, 2013
    Inventor: Chi Keung Lee
  • Patent number: D690374
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 24, 2013
    Inventor: Chi Keung Lee
  • Patent number: D690778
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: October 1, 2013
    Inventor: Chi Keung Lee
  • Patent number: D699807
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 18, 2014
    Inventor: Chi Keung Lee
  • Patent number: D701272
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 18, 2014
    Inventor: Chi Keung Lee
  • Patent number: D828881
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 18, 2018
    Inventor: Chi Keung Lee