Abstract: One aspect provides a printed circuit board (PCB). The PCB can include a plurality of layers and a plurality of plated through-hole (PTH) vias extending through the plurality of layers. The plurality of layers can include at least a top layer for mounting components, a second surface layer, and a first power layer positioned between the top layer and the second surface layer. The plurality of PTH vias can include at least one power via coupled to the first power layer to provide power to components mounted on the top layer. A stub length of the power via can be less than a distance between the power layer and the second surface layer.

Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.

Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.

Abstract: A dual-path signal interconnect is provided. The interconnect can include a first signal trace, first and second solder pads positioned above and connected to the first signal trace, and a third solder pad. The second solder pad separates from the first solder pad. The third solder pad separates from the second solder pad and is connected to a second signal trace. The first and second solder pads are to allow a pin of a connector to be soldered to the first and second solder pads, such that, when the pin of the external connector is soldered, high-speed electrical signals from the first signal trace are routed to the connector. The second and third solder pads are to allow a conductor to be soldered to the second and third solder pads, such that, when the conductor is soldered, the high-speed electrical signals are routed to the second signal trace.

Abstract: Over-terminating the differential mode impedance of a differential transmission line, such as an INFINIBAND™ cable, at the receiving end, improves the differential signal integrity for typical variations in termination network impedance component (e.g., resistor) and transmission line characteristics. Eye opening of the differential signal can be made larger with reduced attenuation but increased jitter compared to under-terminating the differential mode impedance. Because the differential signal quality (larger eye opening) is improved, data can be transmitted over a longer transmission line with the same transmitter and receiver.

Abstract: A computer system and method in which an electrically controlled “hoodlock,” which prevents the computer's chassis from unauthorized opening, can be remotely accessed through powerline communications.

Abstract: A computer-system includes a memory bus, a connector and a controller. The connector is configured to receive a memory module and prevent removal of the memory module from the connector in a first state. The connector allows removal of the memory module from the connector in a second state. The controller is configured to change a connection status between the connector and the memory bus in response to the connector changing from one of the states to the other state. A central processing unit of the computer system is configured to use the memory bus to store data in the memory module.

Abstract: Over-terminating the differential mode impedance of a differential transmission line, such as an INFINIBAND™ cable, at the receiving end, improves the differential signal integrity for typical variations in termination network impedance component (e.g., resistor) and transmission line characteristics. Eye opening of the differential signal can be made larger with reduced attenuation but increased jitter compared to under-terminating the differential mode impedance. Because the differential signal quality (larger eye opening) is improved, data can be transmitted over a longer transmission line with the same transmitter and receiver.

Abstract: A method and system of intrachassis computer component command and control. The existing power rail is used as network connectivity. Further, the CEBus standard (or a CEBus standard modified for the particular power bus) is used to provide platform management functionality. This management functionality is similar to that provided by the proposed IPMI specification. However, the management functionality is implemented intrachassis, that is, it is applied to the internal components of the machine. Particularly advantageous functions, such as rollcall enumeration and command authentication and verification, are included in a preferred embodiment. Further, because these innovative techniques utilize the existing power rail, no additional external cables are required.

Abstract: A method and system of interchassis and intrachassis computer component command and control. The existing power rail is used for network connectivity for intrachassis command and control. An existing common power mains can be used for interchassis command and control. Further, a protocol, for example, the Consumer Electronic Bus (CEBus) protocol (or a CEBus protocol modified for the particular power rail) can be used to provide interchassis and intrachassis platform management functionality. This management functionality is similar to that provided by the proposed Intelligent Platform Management Interface (IPMI) specification. A chassis bridge controller is used to interface the intrachassis power rail command and control infrastructure to an exterior network. External systems (interchassis communications) can communicate to the bridge via the particular protocol over an existing common power mains as a secondary channel exterior network.

Abstract: Control is switched from a first server to a second server in a fault tolerant system. The first and second servers are coupled with an expansion bus in an expansion box for communication with the expansion bus. An indication is provided to the second server to indicate the activity state of the first server. Communication between the first server and the expansion box is disabled if the indication indicates the first server is inactive. Communication between the second server and the expansion bus is disabled if the indication indicates that the first server is active. Communication between the second server is enabled if the indication indicates that the first server is inactive. The indication includes a heartbeat message transmitted periodically to the second server. The expansion bus includes a PCI bus.

Abstract: A protection circuit for a computer system having PCI expansion cards and PCI expansion slots with multiple power rails for supplying power to the PCI expansion cards, the protection circuit including a current monitor that monitors the current levels drawn by the PCI expansion card at each power rail; an inrush current controller for controlling the initial current applied to each of the power rails when an expansion card is initially inserted into an expansion slot; a voltage monitor that monitors the voltage levels applied to selected power rails; and a disconnector for disconnecting the power to the PCI expansion slot when either the current level drawn by the PCI expansion card at any of the power rails goes beyond a selected range or when the voltage levels at any of the selected monitored power rails are below a selected threshold or when commanded by the computer system.

Abstract: A computer system which corrects errors in a second level cache controller. The cache controller erroneously provides the cycle lock signal for the entire period of a writeback cycle followed by an I/O bus access, thus causing a deadlock if an I/O bus master needs access to the host bus at the same time. A circuit determines when the writeback cycle is occurring and masks the lock signal during the writeback operation, so that the long lock assertion is not present and the arbiters can properly control the access to the buses.