Patents by Inventor Chi Ko
Chi Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12009262Abstract: A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region.Type: GrantFiled: May 9, 2022Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng, Kuang-Yao Lo
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Publication number: 20240178059Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.Type: ApplicationFiled: February 2, 2024Publication date: May 30, 2024Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
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Publication number: 20240178321Abstract: A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.Type: ApplicationFiled: January 16, 2024Publication date: May 30, 2024Inventors: Wan-Yi Kao, Chung-Chi Ko
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Patent number: 11992525Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).Type: GrantFiled: November 3, 2023Date of Patent: May 28, 2024Assignee: ACADEMIA SINICAInventors: Chi-Huey Wong, Hsin-Yu Liao, Shih-Chi Wang, Yi-An Ko, Kuo-I Lin, Che Ma, Ting-Jen Cheng
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Publication number: 20240162431Abstract: A core-shell particle includes a core having a chemical structure of Ti(1-x)M1xNb(2-y)M2yO(7-z)Qz, in which M1 is Li or Mg; M2 is Fe, Mn, V, Ni, Cr, or Cu; Q is F, Cl, Br, I, or S; x is 0 to 0.15; y is 0 to 0.15; and z is 0 to 2; and a shell layer wrapping at least a portion of the surface of the core, and the shell layer includes Cu, Nb, Ti, and O.Type: ApplicationFiled: November 28, 2022Publication date: May 16, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kuan-Yu KO, Chun-Chi TSENG, Chia-Erh LIU
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Patent number: 11985853Abstract: A display panel and a display device are provided. The display panel includes a first display area and a second display area, wherein the display panel includes: a base substrate; a plurality of first repeating units arranged on the base substrate in an array and located in the first display area, each of the first repeating units including at least a first sub-pixel; a plurality of second repeating units arranged on the base substrate in an array and located in the second display area, each of the second repeating units including at least a second sub-pixel, wherein a color of light emitted by the first sub-pixel is the same as a color of light emitted by the second sub-pixel; a pixel defining layer disposed on the base substrate and located in both the first display area and the second display area, wherein the pixel defining layer includes a first opening located in the first display area and a second opening located in the second display area.Type: GrantFiled: April 30, 2020Date of Patent: May 14, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Youngyik Ko, Chi Yu, Wei Zhang, Yu Zhang, Weiyun Huang
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Publication number: 20240153828Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.Type: ApplicationFiled: January 18, 2024Publication date: May 9, 2024Inventors: Shu Ling Liao, Chung-Chi Ko
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Publication number: 20240153814Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.Type: ApplicationFiled: January 6, 2024Publication date: May 9, 2024Inventors: Yi-Wen PAN, You-Lan LI, Chung-Chi KO
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Patent number: 11955664Abstract: A battery module includes an insulating base, a pair of electrodes and multiple battery packs. Each electrode is installed to the insulating base and has a bridge portion and a wire connecting part exposed from the insulating base, and a pair of lugs is extended smoothly from each battery pack, and an end of at least a part of the lugs is attached to each bridge portion correspondingly. Therefore, the lug is not being twisted or deformed easily, and the battery module may have good conductive efficiency, long service life, and convenience of changing the battery pack.Type: GrantFiled: March 17, 2022Date of Patent: April 9, 2024Assignee: AMITA TECHNOLOGIES INC.Inventors: Chueh-Yu Ko, Hou-Chi Chen, Chia-Wen Yen, Ming-Hsiao Tsai
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Patent number: 11948841Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.Type: GrantFiled: April 21, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yi Kao, Chung-Chi Ko
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Patent number: 11949014Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first, second, third and fourth fin structures over a substrate. The first and the second fin structures have a first and a second sidewall surfaces respectively. The third and the fourth fin structure have a third and a fourth sidewall surfaces respectively. The first and the second sidewall surfaces extend along a first direction. The third and the fourth sidewall surfaces extend along a second direction different from the first direction. A first and a second isolation structures are over the substrate and surrounding the first and the second fin structure and surrounding the third and the fourth fin structures respectively. A distance between top portions of the third and the fourth sidewall surfaces is greater than that between top portions of the first and the second sidewall surfaces.Type: GrantFiled: April 18, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng
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Publication number: 20240100147Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).Type: ApplicationFiled: November 3, 2023Publication date: March 28, 2024Inventors: Chi-Huey WONG, Hsin-Yu LIAO, Shih-Chi WANG, Yi-An KO, Kuo-I LIN, Che MA, Ting-Jen CHENG
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Patent number: 11935752Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.Type: GrantFiled: March 12, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Yun Peng, Chung-Chi Ko, Keng-Chu Lin
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Publication number: 20240090294Abstract: A display substrate and a display device are provided, the display substrate includes a first display region, and the display substrate includes a plurality of first pixel structures arranged on a base substrate in an array in a first direction and a second direction, where the plurality of first pixel structures are in the first display region, at least one first pixel structure includes at least two first sub-pixels and at least two second sub-pixels, the first sub-pixel includes a first opening, and the second sub-pixel includes a second opening.Type: ApplicationFiled: August 10, 2022Publication date: March 14, 2024Inventors: Chi Yu, Benlian Wang, Hongli Wang, Weiyun Huang, Ming Hu, Youngyik Ko
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Patent number: 11929329Abstract: A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.Type: GrantFiled: May 28, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Ming-Tsung Lee
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Patent number: 11929281Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.Type: GrantFiled: September 21, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
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Patent number: 11923294Abstract: An interconnect structure includes an etching stop layer, a dielectric layer and an insert layer and a conductive line. The insert layer is located between the etching stop layer and the dielectric layer. The conductive line extends through the dielectric layer, the insert layer, and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.Type: GrantFiled: April 29, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
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Patent number: 11918641Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).Type: GrantFiled: May 7, 2021Date of Patent: March 5, 2024Assignee: ACADEMIA SINICAInventors: Chi-Huey Wong, Hsin-Yu Liao, Shih-Chi Wang, Yi-An Ko, Kuo-I Lin, Che Ma, Ting-Jen Cheng
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Patent number: 11908750Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.Type: GrantFiled: May 28, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu Ling Liao, Chung-Chi Ko
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Patent number: 11901219Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.Type: GrantFiled: August 19, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen Pan, You-Lan Li, Chung-Chi Ko