Abstract: The present invention provides a reconfigurable single-inductor multiport converters comprising a single inductor, a primary input port, a primary output port and a plurality of reconfigurable cells, each including a bidirectional port which is reconfigurable to be an auxiliary input port configured to share the inductor and work with the inductor to form an input cell or an auxiliary output port configured to work with a corresponding capacitor to form an output cell; and a plurality of switches arranged for facilitating the bidirectional port to act as auxiliary input port or auxiliary output port; and regulating bidirectional power flowing through the bidirectional port. The present invention provides a simple and low-cost solution for integrating multiple sources and loads simultaneously. The adoption of single-inductor design minimizes the use of magnetic components and the independent output cells configuration avoids cross-regulation problem among output ports, which simplifies the control design.

Abstract: The present invention provides a reconfigurable single-inductor multiport converters comprising a single inductor, a primary input port, a primary output port and a plurality of reconfigurable cells, each including a bidirectional port which is reconfigurable to be an auxiliary input port configured to share the inductor and work with the inductor to form an input cell or an auxiliary output port configured to work with a corresponding capacitor to form an output cell; and a plurality of switches arranged for facilitating the bidirectional port to act as auxiliary input port or auxiliary output port; and regulating bidirectional power flowing through the bidirectional port. The present invention provides a simple and low-cost solution for integrating multiple sources and loads simultaneously. The adoption of single-inductor design minimizes the use of magnetic components and the independent output cells configuration avoids cross-regulation problem among output ports, which simplifies the control design.

Abstract: The present invention discloses a current-source-output light-emitting-diode (LED) driver based on LCLC circuit to provide a constant output current regardless of variations in LED parameters. In the LCLC circuit, the number of additional capacitors is scalable with the number of LED strings for current balancing. Moreover, the input impedance of the improved LCLC circuit is designed to be resistive at the operating frequency to minimize reactive power. The conventional duty cycle control can easily incorporate zero-voltage-switching (ZVS).

Abstract: The present invention discloses a current-source-output light-emitting-diode (LED) driver based on LCLC circuit to provide a constant output current regardless of variations in LED parameters. In the LCLC circuit, the number of additional capacitors is scalable with the number of LED strings for current balancing. Moreover, the input impedance of the improved LCLC circuit is designed to be resistive at the operating frequency to minimize reactive power. The conventional duty cycle control can easily incorporate zero-voltage-switching (ZVS).

Abstract: An approximated lower-triangle structure for the parity-check matrix of low-density parity-check (LDPC) codes which allows linear-time-encoding complexity of the codes is disclosed, and the parity part of the parity-check matrix is semi-deterministic which allows high flexibility when designing the LDPC codes in order to provide higher error-correction capabilities than a typical dual-diagonal structure.

Abstract: A method for encoding data, the method comprising: creating m parity bits from k data bits based on a parity-check matrix (40), the parity-check matrix (40) including a data portion (41) and a parity portion (42), the parity portion (42) includes sub-block matrices, each sub-block matrix being any one from the group consisting of: zero matrix, identity matrix and permutation matrix; and forming a codeword containing the k data bits and the created m parity bits; wherein an upper diagonal is defined in the parity portion (42) starting from the first sub-block matrix in the second column extending to the second last sub-block matrix in the last column, and each sub-block matrix on the upper diagonal is an identity matrix or a permutation matrix, and the sub-block matrices (44) above the upper diagonal are zero matrices; each column from the second column to the third last column of the parity portion (42) contains one or more identity matrices or permutation matrices below the upper diagonal (45) and the remain

Abstract: Digital communication schemes using chaotic signals as carriers can be broadly classified into two categories. In the first category, the chaotic signals carrying the information have to be synchronously regenerated at the receiver, which may be applicable to low noise environment. The second category requires no synchronous regeneration of the carrying chaotic signals in the receiver. An example of the second category utilizes a specific bit structure, which may not be able to resist unintended reception because the fabricated bit structure can be relatively easily detected. This invention involves systems and methods for transmitting digital messages modulated as chaotic signals, and the demodulation methods. One individual chaotic signal generator having a specific chaotic characteristic value is responsible for generating a chaotic signal for each possible value of the digital message according to a chaotic algorithm.

Abstract: A digital communication system based on the use of chaotic carriers is disclosed. For each symbol to be sent, the transmitter sends a reference chaotic signal followed by a transformed version of the reference chaotic signal. For different symbols, different transformations are performed. Also, the transformations are designed such that the transformed versions of the reference chaotic signal do not resemble the original reference chaotic signal. As a consequence, little information can be deduced by inspecting the frequency spectrum of the transmitted signal. Moreover, even if the communication could be detected, it is difficult to decode the messages because there are numerous transformations possible.

Abstract: A digital communication system based on the use of chaotic carriers is disclosed. For each symbol to be sent, the transmitter sends a reference chaotic signal followed by a transformed version of the reference chaotic signal. For different symbols, different transformations are performed. Also, the transformations are designed such that the transformed versions of the reference chaotic signal do not resemble the original reference chaotic signal. As a consequence, little information can be deduced by inspecting the frequency spectrum of the transmitted signal. Moreover, even if the communication could be detected, it is difficult to decode the messages because there are numerous transformations possible.

Abstract: Digital communication schemes using chaotic signals as carriers can be broadly classified into two categories. In the first category, the chaotic signals carrying the information have to be synchronously regenerated at the receiver, which may be applicable to low noise environment. The second category requires no synchronous regeneration of the carrying chaotic signals in the receiver. An example of the second category utilizes a specific bit structure, which may not be able to resist unintended reception because the fabricated bit structure can be relatively easily detected. This invention involves systems and methods for transmitting digital messages modulated as chaotic signals, and the demodulation methods. One individual chaotic signal generator having a specific chaotic characteristic value is responsible for generating a chaotic signal for each possible value of the digital message according to a chaotic algorithm.

Abstract: The fast transient load corrector is a circuit that attaches to the output terminals of a switching converter. Requiring no feedback circuit that interacts with any control parameter of the switching regulator, the fast transient load corrector works independently to improve the transient response of any switching regulator. Effectively the fast transient load corrector combines with the actual load to form a slowly varying composite load which permits the switching converter to maintain a well regulated output voltage or a voltage of pre-defined waveform. The conceptual construction consists of a bi-directional controlled current source and either a voltage sensor or a current sensor. The voltage or current sensor measures the amount of load disturbance and triggers the bi-directional controlled current source to supply transient current to the load. The quantity to be sensed can be the output voltage, the rate of change of the output voltage, or the rate of change of the output current.