Abstract: The present invention discloses a transceiver apparatus having phase-tracking mechanism. A phase detection circuit of a receiver circuit performs sampling and phase detection on an input data signal according to a sampling clock signal to generate a phase detection result. A proportional gain circuit of the receiver circuit applies a proportional gain operation on the phase detection result to generate a phase adjusting signal. A CDR circuit of the receiver circuit receives a source clock signal to generate the sampling clock signal and performs phase-adjusting according to the phase adjusting signal. The integral gain circuit apples an integral gain operation on the phase detection result to generate a frequency adjusting signal. The source clock generating circuit receives a reference clock signal to generate the source clock signal and perform frequency-adjusting according to the frequency adjusting signal. The transmitter circuit performs signal transmission according to the source clock signal.

Abstract: A device comprises: a first spiral coil laid out on a first metal layer of a multi-layer structure, the first spiral coil spiraling inward from a first end to a second end in a clockwise direction from a first perspective that is perpendicular to the first metal layer; a second spiral coil laid out on the first metal layer, the second spiral coil spiraling outward from a third end to a fourth end in a counterclockwise direction from the first perspective, wherein the first spiral coil and the second spiral coil are substantially symmetrical with respect to a central line perpendicular to the multi-layer structure; a twin-spiral coil laid out on a second metal layer of the multi-layer structure, the twin-spiral coil spiraling outward from a fifth end to the central line in a clockwise direction from the first perspective and then spiraling inward from the central line to a sixth end in a counterclockwise direction from the first perspective, wherein the twin-spiral coil is substantially symmetrical with respec

Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a control signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a high-speed pin of a multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad.

Abstract: Disclosed is a clock data recovery (CDR) device including a master lane circuit and a plurality of slave lane circuits. The master lane circuit includes: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO), and a loop divider; a master lane sampling circuit; a master lane phase detector (PD); and a master lane multiplexer coupled between the master lane PD and the CP and between the PFD and the CP. Each slave lane circuit includes: a slave lane sampling circuit (SLS); a slave lane PD; a slave lane digital loop filter; a phase rotator (PR); and a slave lane multiplexer coupled between the VCO and the SLS and between the PR and the SLS, in which the master lane multiplexer and the slave lane multiplexers are configured to have the CDR device operate in one of multiple modes.

Abstract: Disclosed is a Serializer/Deserializer physical layer circuit (SerDes PHY) for receiving and transmitting data in a half-duplex manner, the SerDes PHY including: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a low pass filter, a voltage-controlled oscillator (VCO) and a loop divider; a sampling circuit sampling a received signal according to clocks from the VCO in a receive mode; a phase detector (PD) operating according to outputs of the sampling circuit; a multiplexer connecting the PD with the CP and disconnecting the PFD from the CP in the receive mode, and connecting the PFD with the CP and disconnecting the PD from the CP in a transmission mode; a parallel-to-serial converter converting parallel data into serial data according a clock from the VCO in the transmission mode; and a transmission driver outputting a transmission signal according to the serial data in the transmission mode.

Abstract: Disclosed is a Serializer/Deserializer physical layer circuit (SerDes PHY) for receiving and transmitting data in a half-duplex manner, the SerDes PHY including: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a low pass filter, a voltage-controlled oscillator (VCO) and a loop divider; a sampling circuit sampling a received signal according to clocks from the VCO in a receive mode; a phase detector (PD) operating according to outputs of the sampling circuit; a multiplexer connecting the PD with the CP and disconnecting the PFD from the CP in the receive mode, and connecting the PFD with the CP and disconnecting the PD from the CP in a transmission mode; a parallel-to-serial converter converting parallel data into serial data according a clock from the VCO in the transmission mode; and a transmission driver outputting a transmission signal according to the serial data in the transmission mode.

Abstract: Disclosed is a clock data recovery (CDR) device including a master lane circuit and a plurality of slave lane circuits. The master lane circuit includes: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO), and a loop divider; a master lane sampling circuit; a master lane phase detector (PD); and a master lane multiplexer coupled between the master lane PD and the CP and between the PFD and the CP. Each slave lane circuit includes: a slave lane sampling circuit (SLS); a slave lane PD; a slave lane digital loop filter; a phase rotator (PR); and a slave lane multiplexer coupled between the VCO and the SLS and between the PR and the SLS, in which the master lane multiplexer and the slave lane multiplexers are configured to have the CDR device operate in one of multiple modes.

Abstract: A device comprises: a first spiral coil laid out on a first metal layer of a multi-layer structure, the first spiral coil spiraling inward from a first end to a second end in a clockwise direction from a first perspective that is perpendicular to the first metal layer; a second spiral coil laid out on the first metal layer, the second spiral coil spiraling outward from a third end to a fourth end in a counterclockwise direction from the first perspective, wherein the first spiral coil and the second spiral coil are substantially symmetrical with respect to a central line perpendicular to the multi-layer structure; a twin-spiral coil laid out on a second metal layer of the multi-layer structure, the twin-spiral coil spiraling outward from a fifth end to the central line in a clockwise direction from the first perspective and then spiraling inward from the central line to a sixth end in a counterclockwise direction from the first perspective, wherein the twin-spiral coil is substantially symmetrical with respec

Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a logical signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a pin of a multi-lane, multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad, wherein the external processor is configured to process an electrical signal at the second port in accordance with a first protocol when the logical signal is asserted, and the internal processor is configured to

Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a logical signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a pin of a multi-lane, multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad, wherein the external processor is configured to process an electrical signal at the second port in accordance with a first protocol when the logical signal is asserted, and the internal processor is configured to

Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a control signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a high-speed pin of a multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad, wherein the external processor is configured to process an electrical signal at the second port in accordance with a first protocol when the control signal is asserted, and the internal processor is configured to p

Abstract: An apparatus includes: a laser driver configured to output a laser diode current in accordance with a transmit data, a bias control code, and a modulation control code, a laser diode configured to receive the laser diode current and output a light signal, a photodiode configured to receive the light signal and output a photodiode current, a reference driver configured to output a reference current in accordance with the transmit data, the transmit enable signal, a reference bias code, and a reference modulation code, a two-fold comparison circuit configured to compare the photodiode current and the reference current and output a first decision and a second decision, and a DSP configured to adjust the bias control code and the modulation control code in accordance with the first decision and a second decision. A method provides reliable light output using the described apparatus.

Abstract: An apparatus having a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal, an analog phase detector configured to receive the third clock and the fourth clock and output an analog timing error signal, a filtering circuit configure to receive the analog timing error signal and output an oscillator control signal, a controllable oscillator configured to receive the oscillator control signal and output a fifth clock, a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor, a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor, a digital phase detector configured to receive the third clock and the fourth clock and output a dig

Abstract: A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise a

Abstract: A serial data link receiver and method are provided. In one implementation, the receiver includes a first equalizer for receiving a first received signal and outputting a first equalized signal, and a second equalizer for receiving a second received signal and outputting a second equalized signal. The receiver further includes an analog CDR (clock-data recovery) circuit for receiving the first equalized signal and outputting a first recovered bit stream and a first recovered clock generated in accordance with an analog control voltage, and a digital CDR circuit for receiving the second equalized signal and the first recovered clock and outputting a second recovered bit stream and a second recovered clock based on selecting a phase of the first recovered clock in accordance with a digital phase selection signal.

Abstract: A serial data link receiver and method are provided. In one implementation, the receiver includes a first equalizer for receiving a first received signal and outputting a first equalized signal, and a second equalizer for receiving a second received signal and outputting a second equalized signal. The receiver further includes an analog CDR (clock-data recovery) circuit for receiving the first equalized signal and outputting a first recovered bit stream and a first recovered clock generated in accordance with an analog control voltage, and a digital CDR circuit for receiving the second equalized signal and the first recovered clock and outputting a second recovered bit stream and a second recovered clock based on selecting a phase of the first recovered clock in accordance with a digital phase selection signal.

Abstract: An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: generating an output current with a modulation pattern determined by a transmit data and a transmit enable signal, and a modulation level determined by a first control code and a second control code, wherein a light signal is generated in response to the output current; generating a first decision based on a comparison between a photodiode current and the first reference current, a second decision based on a comparison between the photodiode current and the second reference current, wherein the photodiode current is generated in accordance to the light signal; and generating the first control code and the second control code in response to the first decision and the second decision.

Abstract: An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: generating an output current with a modulation pattern determined by a transmit data and a transmit enable signal, and a modulation level determined by a first control code and a second control code, wherein a light signal is generated in response to the output current; generating a first decision based on a comparison between a photodiode current and the first reference current, a second decision based on a comparison between the photodiode current and the second reference current, wherein the photodiode current is generated in accordance to the light signal; and generating the first control code and the second control code in response to the first decision and the second decision.

Abstract: A digitally controlled oscillator provides high resolution in frequency tuning by using a digitally controlled capacitive network that includes a tunable capacitive circuit, a first capacitor and a second capacitor. The tunable capacitive circuit generates a variable capacitance according to a digital control word. The first capacitor is coupled in an electrically parallel configuration with the tunable capacitive circuit. The second capacitor is coupled in an electrically serial configuration with a combination of the first capacitor and the tunable capacitive circuit. The first capacitor and the second capacitor are sized such that an effective capacitance of the digitally controlled capacitor network has a step size that is a fraction of a step size of the variable capacitance in response to an incremental change in the digital control word.

Abstract: A fraction-N frequency divider includes a multi-phase clock generator, a first phase selector, a second phase selector, a glitch-free multiplexer, a control circuit, and a counter. The multi-phase clock generator is used for generating a plurality of clock signals with different phases. The first phase selector selects one of the clock signals as a first clock signal according to a first phase selecting signal. The second phase selector selects one of the clock signals as a second clock signal according to a second phase selecting signal. The glitch-free multiplexer is used for selectively outputting one of the first and second clock signals. The control circuit generates the first and second phase selecting signals and controls the clock switching timing of the glitch-free multiplexer according to a divisor setting. The counter is used for generating a frequency-divided signal according to the output of the glitch-free multiplexer.