Patents by Inventor Chi Li

Chi Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250138144
    Abstract: A time division duplexed (TDD) frequency modulation continuous wave (FMCW) radar system includes P transmitter circuit chains and M receiver circuit chains. The P transmitter circuit chains are used to transmit a plurality of FMCW signals. A pth transmitter circuit chain is coupled to a single pole Op throw (SPQPT) radio frequency (RF) switch, the SPOT RF switch is coupled to Op antennas, Qp and P are positive integers, and p is a positive integer not larger than P. The M receiver circuit chains are used to receive a plurality of reflected FMCW signals. An mth receiver circuit chain is coupled to a single pole Nm throw (SPNmT) radio frequency (RF) switch, the SPNmT RF switch is coupled to Nm antennas, Nm and M are positive integers, and m is a positive integer not larger than M.
    Type: Application
    Filed: September 26, 2024
    Publication date: May 1, 2025
    Applicant: KaiKuTek INC.
    Inventors: Mike Chun-Hung Wang, Yi-Chu Chen, Tun-Yen Liao, Zi-Hao Fu, Hsiang-Chieh Jhan, Yi-Ting Tseng, Chun-Hsuan Kuo, Wei-Chi Li, Sheng-Tse Tai, Wei-Ming Sun, Pei-Ming Cai
  • Publication number: 20250127903
    Abstract: This invention provides amine-linked C3-glutarimide Degronimers and Degrons for therapeutic applications as described further herein, and methods of use and compositions thereof as well as methods for their preparation.
    Type: Application
    Filed: July 16, 2024
    Publication date: April 24, 2025
    Applicant: C4 THERAPEUTICS, INC.
    Inventors: Andrew J. Phillips, Christopher G. Nasveschuk, James A. Henderson, Yanke Liang, Chi-Li Chen, Martin Duplessis, Minsheng He, Kiel Lazarski
  • Publication number: 20250120161
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Patent number: 12269807
    Abstract: The invention relates to crystalline forms of the bis-HCl salt of a compound represented by Structural Formula 1, and pharmaceutical compositions comprising crystalline forms of the bis-HCL salt of a compound represented by Structural Formula 1 described herein. The crystalline forms of the bis-HCl salt of a compound of Structural Formula 1 and compositions comprising the crystalline forms of the compound of Structural Formula 1 provided herein, in particular, crystalline Form I, crystalline Form J, crystalline Form A, and crystalline Form B, or mixtures thereof, can be incorporated into pharmaceutical compositions, which can be used to treat various disorders. Also described herein are methods for preparing the crystalline forms (e.g., Forms I, J, B and A) of the bis-HCl salt of a compound represented by Structural Formula 1.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: April 8, 2025
    Assignee: Tetraphase Pharmaceuticals, Inc.
    Inventors: Danny LaFrance, Philip C. Hogan, Yansheng Liu, Minsheng He, Chi-Li Chen, John Niu
  • Publication number: 20250101037
    Abstract: This invention provides Degronimers that have E3 Ubiquitin Ligase targeting moieties (Degrons) that can be linked to a targeting ligand for a protein that has been selected for in vivo degradation, and methods of use and compositions thereof as well as methods for their preparation. The invention also provides Degrons that can be used to treat disorders mediated by cereblon or an Ikaros family protein, and methods of use and compositions thereof as well as methods for their preparation.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicant: C4 THERAPEUTICS, INC.
    Inventors: Andrew J. Phillips, Christopher G. Nasveschuk, James A. Henderson, Yanke Liang, Minsheng He, Martin Duplessis, Chi-Li Chen
  • Publication number: 20250102621
    Abstract: In a radar sensor, a transmitting antenna is configured to radiate a transmitted RF signal, a receiving antenna is configured to receive a reflected RF signal from a target, and a frontend circuit is configured to calculate the distance between the target and the radar sensor by measuring the frequency shift between the transmitted RF signal and the reflected RF signal. The frontend circuit includes a crystal-less signal synthesizer configured to generate the transmitted RF signal without using a crystal, and a mixer configured to provide an IF-band signal associated with the frequency shift between the transmitted RF signal and the reflected RF signal by mixing the reflected RF signal and the transmitted RF signal.
    Type: Application
    Filed: April 8, 2024
    Publication date: March 27, 2025
    Applicant: KaiKuTek INC.
    Inventors: Mike Chun-Hung Wang, Yi-Chu Chen, Tun-Yen Liao, Yi-Ting Tseng, Wei-Chi Li
  • Publication number: 20250078297
    Abstract: A system and a method for 3D profile measurements using color fringe projection techniques are provided. The system comprises a color fringe pattern, a digital projector, a color photosensitive coupling device, and a processor. When the digital projector projects the color fringe pattern onto an object to generate color projected fringes, the absolute phase of the object can be calculated by using the horizontal displacement of the color projected fringes, thereby improving the measurement accuracy.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 6, 2025
    Inventors: Wei-hung SU, Pei-chi LI
  • Patent number: 12211915
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Patent number: 12180225
    Abstract: This invention provides Degronimers that have E3 Ubiquitin Ligase targeting moieties (Degrons) that can be linked to a targeting ligand for a protein that has been selected for in vivo degradation, and methods of use and compositions thereof as well as methods for their preparation. The invention also provides Degrons that can be used to treat disorders mediated by cereblon or an Ikaros family protein, and methods of use and compositions thereof as well as methods for their preparation.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: December 31, 2024
    Assignee: C4 Therapeutics, Inc.
    Inventors: Andrew J. Phillips, Christopher G. Nasveschuk, James A. Henderson, Yanke Liang, Minsheng He, Martin Duplessis, Chi-Li Chen
  • Publication number: 20240387588
    Abstract: An image sensor package with a multi-step cavity formed in or on a substrate, which includes an image sensor bonded onto bottom of the multi-step cavity, and a cover glass placed and sealed on a lower portion of the multi-step cavity. Lower portion of the multi-step cavity includes at least a first and a second raised-step structures protruding from the bottom of the multi-step cavity, and the cover glass is placed and sealed over the first raised-step structure.
    Type: Application
    Filed: May 19, 2023
    Publication date: November 21, 2024
    Inventors: Wei-Feng Lin, Chi-Chih Huang, En-Chi Li
  • Publication number: 20240355894
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Publication number: 20240282659
    Abstract: A semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. The first heat dissipation plate has a first upper surface and a first lower surface. The first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. The second heat dissipation plate has a second upper surface and a second lower surface. The second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. The heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. The fixture components include fix screws and nuts. The fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.
    Type: Application
    Filed: April 28, 2024
    Publication date: August 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsiang Lao, Yuan-Sheng Chiu, Hung-Chi Li, Shih-Chang Ku, Tsung-Shu Lin
  • Patent number: 12057483
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: August 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Patent number: 12048747
    Abstract: This invention provides amine-linked C3-glutarimide Degronimers for therapeutic applications as described further herein, and methods of use and compositions thereof as well as methods for their preparation, wherein the C3-glutarimide Degronimers have the formula:
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: July 30, 2024
    Assignee: C4 Therapeutics, Inc.
    Inventors: Andrew J. Phillips, Christopher G. Nasveschuk, James A. Henderson, Yanke Liang, Chi-Li Chen, Martin Duplessis, Minsheng He, Kiel Lazarski
  • Patent number: 12028642
    Abstract: A target tracking system includes an observation module, a dynamic tracking module, a control module and an aiming module. The observation module captures an observation frame including a tracked-object image of a tracked-object and an aiming point image and detects a distance between the observation module and the tracked-object. The dynamic tracking module analyzes the observation frame to obtain a lag correction vector between the aiming point image and the tracked-object image, and obtains a feed-forward correction vector according to the lag correction vector and the distance. The control module generates a control command representing the lag correction vector and a control command representing the feed-forward correction vector. The aiming module moves according to the control commands to control the aiming point image to align with the tracked-object image and control the aiming point image to lead the tracked-object image.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: July 2, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Wei Chang, Yi-Ling Lee, Chia-Jung Liu, Yin-Ling Kuo, Feng-Chi Li
  • Publication number: 20240213675
    Abstract: A multifunctional antenna structure includes a substrate, a broadband antenna, a first frequency divider, a second frequency divider, a wireless network module, and a long term evolution module. The first frequency divider can receive an antenna signal from the broadband antenna and output a first primary frequency division signal and a second primary frequency division signal that have different frequency ranges. The second frequency divider can receive the first primary frequency division signal and output secondary frequency division signals that have different frequency ranges. A minimum difference between any two of the secondary frequency division signals that have frequency ranges near each other is greater than or equal to 2 MHz. The wireless network module can send and receive the second primary frequency division signal. The long term evolution module can send and receive the secondary frequency division signals.
    Type: Application
    Filed: April 27, 2023
    Publication date: June 27, 2024
    Inventors: HSIN-CHI LI, SHENG-TE LIN, YUE-XUN LI
  • Patent number: 12017417
    Abstract: A fixture for heat pressing process is applied to a hot pressing machine for hot pressing two elastic plastic pieces so as to manufacture an airbag. The two elastic plastic pieces are disposed between the fixture and the hot pressing machine. The fixture includes a first frame, a second frame and a flexible heat blocking layer. The first frame includes two first brackets, which are separated from each other with a first distance. The second frame includes two second brackets, which are separated from each other with a second distance, and located at two ends of the first brackets, respectively. The flexible heat blocking layer is fixed by the first frame and/or the second frame.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: June 25, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Jen-Hui Chuang, June-Hao Hou, Chi-Li Cheng, Han-Ting Lin
  • Publication number: 20240187544
    Abstract: A target tracking system includes an observation module, a dynamic tracking module, a control module and an aiming module. The observation module captures an observation frame including a tracked-object image of a tracked-object and an aiming point image and detects a distance between the observation module and the tracked-object. The dynamic tracking module analyzes the observation frame to obtain a lag correction vector between the aiming point image and the tracked-object image, and obtains a feed-forward correction vector according to the lag correction vector and the distance. The control module generates a control command representing the lag correction vector and a control command representing the feed-forward correction vector. The aiming module moves according to the control commands to control the aiming point image to align with the tracked-object image and control the aiming point image to lead the tracked-object image.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 6, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Wei CHANG, Yi-Ling LEE, Chia-Jung LIU, Yin-Ling KUO, Feng-Chi LI
  • Patent number: 11996342
    Abstract: A semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. The first heat dissipation plate has a first upper surface and a first lower surface. The first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. The second heat dissipation plate has a second upper surface and a second lower surface. The second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. The heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. The fixture components include fix screws and nuts. The fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsiang Lao, Yuan-Sheng Chiu, Hung-Chi Li, Shih-Chang Ku, Tsung-Shu Lin
  • Patent number: 11979156
    Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: May 7, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Chen Lu, Hsu-Chi Li, Yi-Jan Chen, Boy-Yiing Jaw, Chin-Tang Chuang, Chung-Hung Chen