Patents by Inventor Chi-Li TU

Chi-Li TU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10692969
    Abstract: A semiconductor structure includes a semiconductor substrate, a buried layer, a pair of first well regions, a second well region, a body doped region, and a first heavily doped region. The semiconductor substrate has a first conductivity type. The buried layer is disposed on the semiconductor substrate. The first well regions having the second conductivity type are disposed on the buried layer. The second well region having the first conductivity type is disposed between the first well regions. The body doped region having the first conductivity type is disposed in the second well region. The first heavily doped region having the first conductivity type is disposed in the body doped region. From a top view, the first heavily doped region and the first well regions extend in a first direction, and the first heavily doped region extends beyond the opposite edges of the first well regions.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: June 23, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ting-You Lin, Chi-Li Tu, Shu-Wei Hsu
  • Patent number: 10692786
    Abstract: A semiconductor structure includes a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a chip region and a seal ring region. The first insulating layer is on the substrate. The second insulating layer is on the first insulating layer. The first seal ring structure is in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure includes a stack of metal layers. The second seal ring structure is in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure includes a polysilicon ring structure. The passivation layer is on the second insulating layer and the first seal ring structure.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 23, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-You Lin, Chi-Li Tu, Shin-Cheng Lin, Yu-Hao Ho, Cheng-Tsung Wu
  • Patent number: 10622510
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 14, 2020
    Assignee: Ingentec Corporation
    Inventors: Ya-Li Chen, Chi-Ming Wang, Chia-Wei Tu, Cheng-Yu Chung, Hsiang-An Feng
  • Patent number: 10622509
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 14, 2020
    Assignee: Ingentec Corporation
    Inventors: Ya-Li Chen, Chi-Ming Wang, Chia-Wei Tu, Cheng-Yu Chung, Hsiang-An Feng
  • Patent number: 10381303
    Abstract: Semiconductor device structures are provided. The semiconductor device structures include a semiconductor substrate. The semiconductor device structures also include an inner metal layer disposed on the semiconductor substrate and a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion. The semiconductor device structures further include a passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 13, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-You Lin, Chi-Li Tu
  • Publication number: 20190189836
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: YA-LI CHEN, CHI-MING WANG, CHIA-WEI TU, CHENG-YU CHUNG, HSIANG-AN FENG
  • Publication number: 20190189837
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Application
    Filed: June 19, 2018
    Publication date: June 20, 2019
    Inventors: YA-LI CHEN, CHI-MING WANG, CHIA-WEI TU, CHENG-YU CHUNG, HSIANG-AN FENG
  • Patent number: 10256201
    Abstract: A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chi-Li Tu, Hung-Wei Chen, Shi-Hsiang Lu, Ching-Wen Wang
  • Patent number: 9997510
    Abstract: The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 12, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chi-Li Tu, Ching-Wen Wang, Karuna Nidhi
  • Publication number: 20180122757
    Abstract: A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 3, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chi-Li TU, Hung-Wei CHEN, Shi-Hsiang LU, Ching-Wen WANG
  • Patent number: 9929114
    Abstract: A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first metal pattern layer is embedded in the dielectric layer and directly below the bonding pad. The first metal pattern layer includes a first body portion and first island portions. The first body portion has first openings in a central region of the first body portion and second openings arranged along a peripheral region of the first body portion and surrounding the first openings. The first island portions are correspondingly disposed in the second openings and spaced apart from the first body portion. First interconnect structures are disposed in the dielectric layer and correspond to the first island portions, such that the bonding pad is electrically connected to the first island portions.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: March 27, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chi-Li Tu, Hung-Wei Chen, Shi-Hsiang Lu, Ching-Wen Wang
  • Publication number: 20180005942
    Abstract: Semiconductor device structures are provided. The semiconductor device structures include a semiconductor substrate. The semiconductor device structures also include an inner metal layer disposed on the semiconductor substrate and a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion. The semiconductor device structures further include a passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ting-You LIN, Chi-Li TU
  • Publication number: 20170069620
    Abstract: The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.
    Type: Application
    Filed: September 9, 2015
    Publication date: March 9, 2017
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chi-Li TU, Ching-Wen WANG, Karuna NIDHI