Abstract: A verification apparatus and a verification method are suitable for a touch display panel which comprises multiple partitions. The verification apparatus includes signal generating circuit and verification switch circuit. The signal generating circuit is configured to generate a verification voltage. The verification switch circuit comprises multiple switch units which are separately coupled to the partitions and the signal generating circuit, and are configured to deliver verification voltage simultaneously to at least two of multiple partitions.

Abstract: A gate driving circuit is provided. The gate driving circuit includes multistage driving modules, where an Nth stage driving module includes a setting circuit, a first driving circuit, an isolating switch circuit, a second driving circuit and an anti-noise circuit. The setting circuit generates a first precharge signal according to a gate driving signal of an (N?2)th scan line or a start signal. The isolating switch circuit coupled between the first driving circuit and the second driving circuit provides a second precharge signal, so as to effectively avoid a flickering problem of a display image caused by a surge of the gate driving signal due to a coupling effect of a parasitic capacitance of the transistor and a bootstrap capacitor, and meanwhile the bootstrap capacitor is not used, so as to effectively reduce a bezel area.

Abstract: A gate driving circuit is provided. The gate driving circuit includes multistage driving modules, where an Nth stage driving module includes a setting circuit, a first driving circuit, an isolating switch circuit, a second driving circuit and an anti-noise circuit. The setting circuit generates a first precharge signal according to a gate driving signal of an (N?2)th scan line or a start signal. The isolating switch circuit coupled between the first driving circuit and the second driving circuit provides a second precharge signal, so as to effectively avoid a flickering problem of a display image caused by a surge of the gate driving signal due to a coupling effect of a parasitic capacitance of the transistor and a bootstrap capacitor, and meanwhile the bootstrap capacitor is not used, so as to effectively reduce a bezel area.

Abstract: A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.

Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract: A verification apparatus and a verification method are provided in this disclosure. The verification apparatus is suitable for touch display panel which comprises multiple partitions. The verification apparatus includes signal generating circuit and verification switch circuit. The signal generating circuit is configured to generate verification voltage. The verification switch circuit comprises multiple switch units which is separately coupled to the partitions and the signal generating circuit, and is configured to deliver verification voltage simultaneously to a least two of multiple partitions.

Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract: The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract: An in-cell touch display panel includes an active device array substrate, an opposite substrate and a display medium layer. The active device array substrate includes a substrate, a plurality of active devices, a plurality of pixel electrodes, a plurality of common electrodes, a plurality of data signal lines and a plurality of switches. The pixel electrodes are respectively electrically connected to the corresponding active devices. The common electrodes are arranged into a plurality of common electrode series, wherein every two or more common electrode series are connected to each other to form a first touch electrode. The data signal lines are respectively coupled to the pixel electrodes through the corresponding active devices. Every two or more of the data signal lines are electrically connected to one of the switches, wherein the pixel electrodes and the data signal lines coupled to a same switch together form a second touch electrode.

Abstract: The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract: A touch light shielding substrate including a first substrate, a patterned light shielding layer disposed above the first substrate, first touch sensing units disposed above the first substrate, and second touch sensing units disposed above the first substrate is provided. The patterned light shielding layer has transparent holes arranged in an array. The first touch sensing units and the second touch sensing units are interlaced with each other. The patterned light shielding layer, the first touch sensing units, and the second touch sensing units are located in the same side of the first substrate. The patterned light shielding layer is disposed between the first touch sensing units and the second touch sensing units, so that the first touch sensing units and the second touch sensing units are electrically independent. Moreover, a touch display apparatus including the touch light shielding substrate is also provided.

Abstract: A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.

Abstract: An in-cell touch display panel includes an active device array substrate, an opposite substrate and a display medium layer. The active device array substrate includes a substrate, a plurality of active devices, a plurality of pixel electrodes, a plurality of common electrodes, a plurality of data signal lines and a plurality of switches. The pixel electrodes are respectively electrically connected to the corresponding active devices. The common electrodes are arranged into a plurality of common electrode series, wherein every two more common electrode series are connected to each other to form a first touch electrode. The data signal lines are respectively coupled to the pixel electrodes through the corresponding active devices. Every two more of the data signal lines are electrically connected to one of the switches, wherein the pixel electrodes and the data signal lines coupled to a same switch together form a second touch electrode.

Abstract: A method of fabricating a semiconductor device includes forming a non-conductive layer over a semiconductor substrate. A low-k dielectric layer is formed over the non-conductive layer. The low-k dielectric layer is etched and stopped at the non-conductive layer to form an opening. A plasma treatment is performed on the substrate to convert the non-conductive layer within the opening into a conductive layer. The opening is filled with a copper-containing material in an electroless copper bottom up fill process to form a copper-containing plug. The copper-containing plug is planarized so that the top of the copper-containing plug is co-planar with the top of the low-k dielectric layer. The substrate is heated to form a self-forming barrier layer on the sidewalls of the copper-containing plug.

Abstract: A touch color filter includes a substrate, a touch sensing layer, a black matrix layer, and a color filter layer. The touch sensing layer is located on the substrate. The black matrix layer is located on the substrate. A boundary of the touch sensing layer is located within a boundary of the black matrix layer. The color filter layer is located on the substrate. The touch sensing layer and the black matrix layer are located between the substrate and the color filter layer, and the color filter layer covers the touch sensing layer and the black matrix layer.

Abstract: A method of fabricating a semiconductor device includes forming a non-conductive layer over a semiconductor substrate. A low-k dielectric layer is formed over the non-conductive layer. The low-k dielectric layer is etched and stopped at the non-conductive layer to form an opening. A plasma treatment is performed on the substrate to convert the non-conductive layer within the opening into a conductive layer. The opening is filled with a copper-containing material in an electroless copper bottom up fill process to form a copper-containing plug. The copper-containing plug is planarized so that the top of the copper-containing plug is co-planar with the top of the low-k dielectric layer. The substrate is heated to form a self-forming barrier layer on the sidewalls of the copper-containing plug.

Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

Abstract: A repairable pixel structure includes a substrate, at least a data line, at least a gate line, a transparent pixel electrode, a TFT, and a transparent pre-repair electrode. The TFT includes a gate, a drain, and a source. The transparent pre-repair electrode is disposed corresponding to the electrode in a vertical direction and is electrically connected to the drain. When a broken circuit occurs in the pixel structure, a laser beam is provided to perform a welding process on the transparent pre-repair electrode for repairing the pixel structure.

Abstract: A structure, a fabrication method and an application of an overlay mark. The overlay mark structure has an outer mark and an inner mark. The outer mark encloses a cross area that has two central axes. The inner mark has four strip patterns arranged in two central axes and extend outwardly towards four directions from the central part of the closed cross area.