Abstract: The present invention allows NIC resources to be accessed through auxiliary power and an ASIC clock while the PC is powered down and while PCI power and the PCI clock are not available. The present invention also provides an alternate path for accessing the NIC registers, downloading keep-alive and alert-on-LAN packets to the transmit packet buffer (TPB), as well as uploading received packets from the receive packet buffer (RPB). The present invention also allows monitoring PCI activity and seamlessly servicing the PCI configuration cycle (when PCI power and the PCI clock are restored) in conjunction with responding to the access through the alternate path (while PCI power and the PCI clock are not available).

Abstract: The present invention provides a device which facilitates communications between a computer system and a data network by buffering data in transit between the computer system and the data network in a single buffer memory which can be flexibly partitioned into separate transmit and receive buffers. This flexible partitioning allows the relative sizes of the transmit and receive buffers to be optimized across a wide range of buses, data networks and network usage patterns. The transmit and receive buffers are structured as ring buffers within respectively allocated portions of the buffer memory. The buffer memory is controlled by a simple finite state machine controller, which is free from the performance impediments and higher cost associated with a microprocessor-based controller. The present invention also provides support for retransmission of packets that encounter transmission problems such as collisions during transmissions on the data network.

Abstract: Support for priority and IP security packets, and other protocols at the network interface level and in conjunction with FIFO-based packet buffers is provided by allowing out of order processing of certain packets in the FIFO. The optimized character of FIFO for sequential transfer is maintained, while particular types of packets are processed out of order to achieve minimum latency and maximum data security in an intelligent network interface card. A buffer stores data packets in an order of receipt. Logic is included in the network interface to transfer packets out of the buffer according to the order of receipt, and according to the respective packet types so that packets having a particular packet type are transferred out of the order of receipt relative to packets having other packet types.

Abstract: A transmit packet buffer device capable of asynchronous read and write functions is used for receiving frame data from a host and forwarding the data over a network. The device comprises dual-ported memory capable of independent write and read access, a plurality of registers for storing address pointers to locations in the memory, and a logic device coupled to the dual-ported memory and the plurality of registers for controlling downloading data into the memory at a first clock speed, and transmitting data from the memory at a second clock speed. The registers are used to store memory addresses for reference by the logic device, and the data is divided into frames.

Abstract: A network transmitter schedules packets so that packets are transmitted to a host or group of hosts so as not to overload any particular part of the network. In an embodiment, the transmitter uses packet data structures with a schedule indication for packets placed in the queue so that an independently running adaptor may know when to remove packets from the queue and transmit them. In an alternative embodiment, packets are scheduled by setting a future interrupt for transmitting a packet or group of packets. In a further embodiment, packets are placed in temporal sets where a temporal set is a group of packets that can be transmitted in succession without violating the bandwidth limitations of any network segment.