Patents by Inventor Chi-Lin CHENG

Chi-Lin CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088025
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 11544301
    Abstract: The disclosure provides an identification method with multi-type input, which is suitable for multiple type input devices. The identification method includes: capturing a corresponding original data through the input devices, and converting the original data into a plurality of structure units correspondingly. Performing a text integration step, deconstructing a text reference element corresponding to the attributes of the structural units based on the structural units and associated elements thereof, and performing a weight evaluation and reconstruction to generate a candidate content according to the text reference element. Making a decision based on the candidate content, outputting the candidate text as a recommended content when the candidate content includes a unique candidate text, and transmitting it to a corresponding output device. An electronic device using the identification method is also provided.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: January 3, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Hao-Yu Hung, Chi-Lin Cheng, Yi-Chi Lai, Tsung-Lun Wu, Ying-Ru Chen, Shih-Xian Yeh
  • Publication number: 20220027393
    Abstract: The disclosure provides an identification method with multi-type input, which is suitable for multiple type input devices. The identification method includes: capturing a corresponding original data through the input devices, and converting the original data into a plurality of structure units correspondingly. Performing a text integration step, deconstructing a text reference element corresponding to the attributes of the structural units based on the structural units and associated elements thereof, and performing a weight evaluation and reconstruction to generate a candidate content according to the text reference element. Making a decision based on the candidate content, outputting the candidate text as a recommended content when the candidate content includes a unique candidate text, and transmitting it to a corresponding output device. An electronic device using the identification method is also provided.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 27, 2022
    Inventors: Hao-Yu HUNG, Chi-Lin CHENG, Yi-Chi LAI, Tsung-Lun WU, Ying-Ru CHEN, Shih-Xian YEH
  • Patent number: 10620649
    Abstract: A current regulating circuit is provided in the invention. The current regulating circuit includes a first inverter, a second inverter, a PMOS, an NMOS and a capacitor. The first inverter receives a control signal. The second inverter receives the control signal. A first gate of the PMOS is coupled to the first inverter. The NMOS is coupled to the PMOS and a second gate of the NMOS is coupled to the second inverter. The capacitor is coupled to the PMOS and the NMOS at a node, and is coupled to a low dropout regulator at a reference node.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: April 14, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Chi-Lin Cheng
  • Publication number: 20190384335
    Abstract: A current regulating circuit is provided in the invention. The current regulating circuit includes a first inverter, a second inverter, a PMOS, an NMOS and a capacitor. The first inverter receives a control signal. The second inverter receives the control signal. A first gate of the PMOS is coupled to the first inverter. The NMOS is coupled to the PMOS and a second gate of the NMOS is coupled to the second inverter. The capacitor is coupled to the PMOS and the NMOS at a node, and is coupled to a low dropout regulator at a reference node.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 19, 2019
    Inventor: Chi-Lin CHENG