Abstract: A color correction system and a colorimeter positioning method therefore are provided. A first color block is displayed in a first display area of a display. During the period of displaying the first color block, a first sensing value is acquired for the first color block through a sensor of a colorimeter. The first sensing value is compared with a first reference value to determine whether the first sensing value meets the first specific condition. In response to the first sensing value meeting the first specific condition, a second color block is displayed in the first display area of the display. During the period of displaying the second color block, a second sensing value is acquired for the second color block through the sensor. The second sensing value is compared with a second reference value to determine whether the second sensing value meets the second specific condition.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable hybrid microcontroller having a state machine and one or more processors. The state machine is configured to generate a first set of execution signals in response to a request to perform memory operations on non-volatile memory cells in the memory system. The first set of execution signals have a format configured to interface with one or more circuits coupled to the non-volatile memory cells. The hybrid microcontroller has an interface that translates the first set of execution signals to instruction identifiers. The one or more processors execute instructions identified by the instruction identifiers to generate a second set of execution signals. The second set of execution signals are provided to the one or more circuits to perform the memory operations on the non-volatile memory cells.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable hybrid microcontroller having a state machine and one or more processors. The state machine is configured to generate a first set of execution signals in response to a request to perform memory operations on non-volatile memory cells in the memory system. The first set of execution signals have a format configured to interface with one or more circuits coupled to the non-volatile memory cells. The hybrid microcontroller has an interface that translates the first set of execution signals to instruction identifiers. The one or more processors execute instructions identified by the instruction identifiers to generate a second set of execution signals. The second set of execution signals are provided to the one or more circuits to perform the memory operations on the non-volatile memory cells.

Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.

Abstract: A voltage detecting device applied to a driving device of a light-emitting diode device is provided. The detecting device includes a voltage inspecting device, an isolating/connecting control device and a comparing device. The voltage inspecting device is coupled to an output terminal of the driving device to inspect a status of an output voltage of the driving device and outputs an inspecting signal. The isolating/connecting control device, coupled between the voltage inspecting device and the driving device, isolates or connects the output terminal of the driving device according to the inspecting signal. The comparing device, composed of low voltage elements, is coupled to the isolating/connecting control device, and compares the output voltage of the driving device with a reference voltage and generates a detecting signal according to the comparing result.

Abstract: A motor controller controlling a rotational speed of a motor and including a thermal detector, a capacitor, an operational amplifier (OP), a charging/discharging circuit, a flip-flop and a logic circuit. The thermal detector detects environmental temperature of the motor to set a first reference voltage. The capacitor has one terminal coupled to a second reference voltage while another terminal thereof is charged/discharged by the charging/discharging circuit, controlled by a pulse width modulation (PWM) signal, to provide a third reference voltage. The OP compares the first and third reference voltages and outputs the comparison result to a ‘set’ terminal of the flip-flop. The flip-flop further uses a ‘reset’ terminal to receive a clock signal and the output signal thereof is utilized in generating the PWM signal. The PWM signal is further provided to the logic circuit for setting a duty cycle of a driving current of the motor.

Abstract: A voltage detecting device applied to a driving device of a light-emitting diode device is provided. The detecting device includes a voltage inspecting device, an isolating/connecting control device and a comparing device. The voltage inspecting device is coupled to an output terminal of the driving device to inspect a status of an output voltage of the driving device and outputs an inspecting signal. The isolating/connecting control device, coupled between the voltage inspecting device and the driving device, isolates or connects the output terminal of the driving device according to the inspecting signal. The comparing device, composed of low voltage elements, is coupled to the isolating/connecting control device, and compares the output voltage of the driving device with a reference voltage and generates a detecting signal according to the comparing result.

Abstract: A motor controller controlling a rotational speed of a motor and including a thermal detector, a capacitor, an operational amplifier (OP), a charging/discharging circuit, a flip-flop and a logic circuit. The thermal detector detects environmental temperature of the motor to set a first reference voltage. The capacitor has one terminal coupled to a second reference voltage while another terminal thereof is charged/discharged by the charging/discharging circuit, controlled by a pulse width modulation (PWM) signal, to provide a third reference voltage. The OP compares the first and third reference voltages and outputs the comparison result to a ‘set’ terminal of the flip-flop. The flip-flop further uses a ‘reset’ terminal to receive a clock signal and the output signal thereof is utilized in generating the PWM signal. The PWM signal is further provided to the logic circuit for setting a duty cycle of a driving current of the motor.

Abstract: A control device for driving a motor which includes a rotor and a stator is provided. The control device includes a Hall detector and driving circuit. The Hall detector detects magnetic flux variation when the rotor rotates and generates a first detection signal and a second detection signal. The first and second detection signals represent current rotation location when the rotor rotates. The driving circuit generates a driving signal to drive the stator. The driving circuit turns on or off the driving signal according to a control signal and the relationship between the first and second detection signals.

Abstract: The invention discloses a motor driving device for generating at least one driving signal according to a clock signal corresponding to the output signal of a hall sensor. The motor driving device also controls rotation of a motor via at least one driving signal, wherein the at least one driving signal includes a first driving signal and a second driving signal and the motor driving device controls the rotation of the motor according to the first driving signal and the second driving signal.

Abstract: A driving device is provided for controlling rotation of a motor. The driving device comprises an inputting module, a comparing module and a processing module. The inputting module includes a first current source, a first voltage source and a first capacitance. The first capacitance is coupled between the first current source and the first voltage source for charging/discharging and generating a voltage signal. The comparing module is coupled to the inputting module for comparing a selecting signal with the voltage signal and generating a comparing signal. The processing module is coupled to the comparing module and generates a control signal according to a clock signal and the comparing signal, wherein the driving device controls the rotation of the motor by the control signal.