Patents by Inventor Chi-Lin HUANG

Chi-Lin HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200310568
    Abstract: A glass structure includes a glass substrate, a first sensing layer, a second sensing layer, a signal wire layer and an insulative layer. Each of the two sensing layers is formed by a metal oxide conductive film electrically connected onto a metal mesh and has sensing columns and isolation columns which insulatively separate the sensing columns. An end of each of the sensing columns is provided with a contact connected to the signal wire layer. Conductive material of each isolation column is divided into disconnected insulative areas. The insulative layer is adhesively disposed between the first and second sensing layers. The sensing columns of the first sensing layers are orthogonal to the second sensing columns on the second sensing layer to constitute a capacitive sensing unit array.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Young Fast Optoelectronics Co., Ltd.
    Inventors: Chih-Chiang Pai, Meng-Kuei Lin, Hung-Chi Huang Huang, Chiu-Wen Chen
  • Patent number: 10789335
    Abstract: A remote diagnosis management system is utilized for a plurality of massage bath devices and includes at least one processor executing steps of: receiving a remote trigger event of each of the massage bath devices, wherein the remote trigger event is generated by a control unit of each of the massage bath devices or by at least one of a maintenance-worker and a user of each of the massage bath devices; analyzing the remote trigger event to generate an analyzed result; remotely operating at least one state of each of the massage bath devices according to the analyzed result; requesting authorization from the user of each of the massage bath devices before the step of remotely operating the at least one state of each of the massage bath devices; and scheduling at least one remote diagnosis of the massage bath devices.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: September 29, 2020
    Assignee: DARTPOINT TECH. CO., LTD.
    Inventors: Chi-Lin Kang, Ai-Chieh Lu, Chao-Yuan Huang
  • Patent number: 10775276
    Abstract: A portable gas detecting device includes at least one detecting chamber, at least one gas sensor and at least one actuator. The gas sensor is disposed in the detecting chamber and configured for monitoring gas inside the detecting chamber. The actuator is disposed in the detecting chamber and includes a piezoelectric actuator. When an actuating signal is applied to the piezoelectric actuator and the piezoelectric actuator generates a resonance effect, the gas outside the detecting chamber is introduced into the detecting chamber for sampling. The actuator is driven by an instantaneous sampling pulse to control a trace of gas to flow into the detecting chamber for forming a stable airflow environment. In the stable airflow environment, a gas molecule is dissolved in or bonded to a reaction material on a surface of the gas sensor for reacting.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 15, 2020
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Chiu-Lin Lee, Ching-Sung Lin, Chi-Feng Huang, Yung-Lung Han, Chun-Yi Kuo
  • Publication number: 20200287100
    Abstract: Disclosed herein are a light-emitting diode (LED) package structure and a method producing the same. The LED package structure includes a substrate; and a light-emitting unit disposed on the substrate. The light-emitting unit comprises a gallium nitride-based semiconductor, and a polymeric layer encapsulating the gallium nitride-based semiconductor. Also disclosed herein is a method of producing the LED package structure. The method comprises: providing a substrate; electrically connecting a gallium nitride-based semiconductor onto the substrate; overlaying the gallium nitride-based semiconductor with a slurry comprising a resin and a plurality of composite fluorescent gold nanocluster; and curing the slurry overlaid on the gallium nitride-based semiconductor to form a solidified polymeric layer.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Applicant: Chung Yuan Christian University
    Inventors: Cheng-An LIN, Yeeu-Chang LEE, Cheng-Yi HUANG, Chi-An CHEN, Yi-Tang SUN
  • Patent number: 10756243
    Abstract: Disclosed herein are a light-emitting diode (LED) package structure and a method producing the same. The LED package structure includes a substrate; and a light-emitting unit disposed on the substrate. The light-emitting unit comprises a gallium nitride-based semiconductor, and a polymeric layer encapsulating the gallium nitride-based semiconductor. Also disclosed herein is a method of producing the LED package structure. The method comprises: providing a substrate; electrically connecting a gallium nitride-based semiconductor onto the substrate; overlaying the gallium nitride-based semiconductor with a slurry comprising a resin and a plurality of composite fluorescent gold nanocluster; and curing the slurry overlaid on the gallium nitride-based semiconductor to form a solidified polymeric layer.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 25, 2020
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Cheng-An Lin, Yeeu-Chang Lee, Cheng-Yi Huang, Chi-An Chen, Yi-Tang Sun
  • Patent number: 10756162
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an adhesive layer over a semiconductor substrate and forming a magnetic element over the adhesive layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes partially removing the adhesive layer such that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element. In addition, the method includes forming a conductive line over the isolation element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng Chen, Wei-Li Huang, Chien-Chih Kuo, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10748810
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive line over a substrate. The method includes forming a first protection cap over a first portion of the first conductive line. The first protection cap and the first conductive line are made of different conductive materials. The method includes forming a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The method includes forming a first opening in the first photosensitive dielectric layer and over the first protection cap. The method includes forming a conductive via structure and a second conductive line over the first conductive line. The conductive via structure is in the first opening and over the first protection cap, and the second conductive line is over the conductive via structure and the first photosensitive dielectric layer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Wei-li Huang, Sheng-Pin Yang, Chi-Cheng Chen, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10741513
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20200243664
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 30, 2020
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Patent number: 10720487
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an etch stop layer over a semiconductor substrate and forming a magnetic element over the etch stop layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes forming a conductive line over the isolation element. In addition, the method includes forming a dielectric layer over the conductive line, the isolation element, and the magnetic element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Publication number: 20200227425
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip having a flash gate structure disposed over a substrate and including a control gate separated from a floating gate by an inter-electrode dielectric. One or more first sidewall spacers laterally surround the flash gate structure. The inter-electrode dielectric is directly between the one or more first sidewall spacers. A logic gate structure is disposed over the substrate and is laterally surrounded by one or more second sidewall spacers having a smaller height than the one or more first sidewall spacers.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventors: Josh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho
  • Patent number: 10700000
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20200178842
    Abstract: Methods and systems are disclosed for the detecting of whether a subject has a lung disorder such as asthma, tuberculosis or lung cancer. Monitoring the subject's health and prognosis is also disclosed.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Li-Peng WANG, Chi-Lin YOUNG, Chien-Lin HUANG, Tsung-Kuan A. CHOU
  • Patent number: 10673813
    Abstract: The present invention provides a method for NAT traversal in VPN so that the VPN can detect the rule of port allocation for NAT outside the VPN to achieve NAT traversal. The communication structure according to the present invention includes a public network, a client network, a destination network, a first NAT, a second NAT. A DNAT-T proxy server is installed between the first NAT and the second NAT and has the function for the VPN to conduct a plurality of (N times) registrations before sending data out to detect the rule for NAT port allocation of the DNAT-T proxy server, and then inform the next NAT port allocation to the other side of the VPN so as to achieve NAT traversal for the data packets in VPN.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 2, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsueh Ming Hang, Shaw Hwa Hwang, Cheng Yu Yeh, Bing Chih Yao, Kuan Lin Chen, Yao Hsing Chung, Shun Chieh Chang, Chi Jung Huang, Li Te Shen, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
  • Publication number: 20200152676
    Abstract: A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 14, 2020
    Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Fang-Ting KUO, Meng-Chang HO, Yu-Lin WEI, Chi-Feng HUANG
  • Publication number: 20200144315
    Abstract: A semiconductor device includes a substrate and an isolation feature. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate, wherein a bottom surface of the second portion is below the top surface of the substrate. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure extends along a top surface of the second portion of the isolation feature.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Fang-Ting KUO, Meng-Chang HO, Yu-Lin WEI, Chi-Feng HUANG
  • Publication number: 20200146095
    Abstract: A UE in a wireless network performs RRM measurements according to power saving schemes. The UE receives Synchronization Signal Blocks (SSBs), which are broadcast periodically from a base station to a cell served by the base station, and receives additional signal blocks transmitted periodically from the base station. The additional signal blocks and the SSBs use different time-and-frequency resources. The UE performs an RRM measurement according to information received within an RRM measurement window including at least one of the additional signal blocks and a corresponding one of the SSBs. Additionally or alternatively, the UE performs RRM measurements on SSBs with a first cycle period equal to a Discontinuous Reception (DRX) cycle period. In response to an indication that a predefined condition for the RRM measurements is satisfied, the UE performs the RRM measurements with a second cycle period which is at least two times of the first cycle period.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 7, 2020
    Inventors: Chi-Hsuan Hsieh, Wei-De Wu, Din-Hwa Huang, Kuan-Lin Chen
  • Publication number: 20200133117
    Abstract: A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.
    Type: Application
    Filed: August 12, 2019
    Publication date: April 30, 2020
    Inventors: WEI-LIN CHU, HSIN-LUN TSENG, SHENG-WEN HUANG, CHIH-CHUNG HUANG, CHI-MING TSAI
  • Publication number: 20200135730
    Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
    Type: Application
    Filed: December 31, 2019
    Publication date: April 30, 2020
    Inventors: Chia-Chung CHEN, Chi-Feng HUANG, Victor Chiang LIANG, Fu-Huan TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH, Han-Min TSAI, Hong-Lin CHU
  • Patent number: 10629605
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Josh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho