Patents by Inventor Chi-Lin Liu

Chi-Lin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11551626
    Abstract: An electronic paper display device and an operation method thereof are provided. The electronic paper display device includes an electronic paper display panel and a timing controller. The timing controller includes a first image buffer memory, a second image buffer memory, and an update buffer memory. The timing controller receives a touch track data. The first image buffer memory and the second image buffer memory are a ping-pong buffer architecture, and receive a video stream in staggered timing. The second image buffer memory receives the touch track data and simultaneously updates a current display screen data stored in the update buffer memory when the first image buffer memory receives the video stream to update the current display screen data into the update buffer memory. The timing controller drives the electronic paper display panel according to the current display screen data.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: January 10, 2023
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Lung Cheng, Shu-Cheng Liu, Pei-Lin Tien, Cheng-Hsin Chu, Chi-Mao Hung
  • Patent number: 11545560
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Patent number: 11527504
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 11526649
    Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheok-Kei Lei, Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li
  • Patent number: 11509306
    Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Greg Gruber, Chi-Lin Liu, Ming-Chang Kuo, Lee-Chung Lu, Shang-Chih Hsieh
  • Patent number: 11508324
    Abstract: An E-paper display device including an E-paper display panel and a display driver is provided. The E-paper display panel displays an image. The image includes a first frame and a second frame. The display driver is coupled to the E-paper display panel. The display driver drives the E-paper display panel to display the image. The display driver drives a first pixel group of the E-paper display panel in a first polarity and drives a second pixel group of the E-paper display panel in a second polarity to display the first frame during a first frame period. The first pixel group and the second pixel group are arranged in interlacing. The display driver drives the second pixel group of the E-paper display panel in the first polarity to display the second frame during a second frame period. Moreover, a method for driving an E-paper display panel is also provided.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 22, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Shu-Cheng Liu, Hsiao-Lung Cheng, Pei-Lin Tien, Chi-Mao Hung
  • Patent number: 11501725
    Abstract: An e-paper display device, including a driver circuit. The driver circuit is coupled to the e-paper display panel and drives the e-paper display panel to display one or more line segments, which include a current display line segment and a target display line segment. During a frame period, the driver circuit pre-drives a display area to display a first color according to the current display line segment. At least part of the target display line segment is located in the display area. During a next frame period, the driver circuit drives a part of the display area excluding the target display line segment to display a second color and a part of the display area including the target display line segment to display the first color according to the target display line segment. A method for driving an e-paper display panel.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: November 15, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Lung Cheng, Shu-Cheng Liu, Pei-Lin Tien, Chi-Mao Hung
  • Publication number: 20220327275
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Publication number: 20220301509
    Abstract: An electronic paper display device and an operation method thereof are provided. The electronic paper display device includes an electronic paper display panel and a timing controller. The timing controller includes a first image buffer memory, a second image buffer memory, and an update buffer memory. The timing controller receives a touch track data. The first image buffer memory and the second image buffer memory are a ping-pong buffer architecture, and receive a video stream in staggered timing. The second image buffer memory receives the touch track data and simultaneously updates a current display screen data stored in the update buffer memory when the first image buffer memory receives the video stream to update the current display screen data into the update buffer memory. The timing controller drives the electronic paper display panel according to the current display screen data.
    Type: Application
    Filed: January 24, 2022
    Publication date: September 22, 2022
    Applicant: E Ink Holdings Inc.
    Inventors: Hsiao-Lung Cheng, Shu-Cheng Liu, Pei-Lin Tien, Cheng-Hsin Chu, Chi-Mao Hung
  • Publication number: 20220302257
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20220291801
    Abstract: A driving circuit of a display and an operation method of a timing controller are provided. The driving circuit of the display includes a timing controller. The timing controller is coupled to a general purpose input/output (GPIO) pin of the touch driver. The timing controller receives an instruction signal via the general purpose input/output pin of the touch driver. The timing controller starts a detection period according to a main falling edge of the instruction signal. The timing controller determines a current operating status of the touch driver according to a number of sub-falling edges of the instruction signal during the detection period.
    Type: Application
    Filed: January 21, 2022
    Publication date: September 15, 2022
    Applicant: E Ink Holdings Inc.
    Inventors: Hsiao-Lung Cheng, Shu-Cheng Liu, Pei-Lin Tien, I-Shin Lo, Chi-Mao Hung
  • Publication number: 20220275505
    Abstract: Methods and apparatus for a baking chamber for processing a chamber component are provided herein. In some embodiments, a baking chamber includes: an enclosure defining a first chamber, wherein the first chamber comprises: a first chamber body having a first floor and first sidewalls that couple the first floor to a first lid of the first chamber body to define a first interior volume; a first support disposed in the first interior volume; a first gas line disposed in the first interior volume proximate the first lid; a first showerhead disposed between the first gas line and the first support; a first exhaust coupled to the first floor; and a first heater disposed in the first interior volume between the first support and the first floor; and wherein the enclosure includes a door configured to facilitate transferring the chamber component into and out of the enclosure.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Chien-Min LIAO, Chi-Feng LIU, Yi Nung WU, Hsiu YANG, Yixing LIN, Boon Sen CHAN, Siamak SALIMIAN
  • Patent number: 11392743
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Publication number: 20220223113
    Abstract: An electronic paper display and a driving method thereof are provided. The electronic paper display includes an electronic paper display panel, a touch panel and a processing circuit. The touch panel outputs a first touch coordinate of a current touch and a second touch coordinate of a next touch. The processing circuit executes a filter module and a line drawing module. The filter module outputs a first measured position data and a first predicted position data to the line drawing module. The line drawing module drives the electronic paper display panel to display a first predicted track. The filter module outputs a second measured position data to the line drawing module. The line drawing module determines whether a second track display coordinate corresponding to the second measured position data is equal to the first predicted display coordinate to correct the first predicted track.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Applicant: E Ink Holdings Inc.
    Inventors: Shu-Cheng Liu, Hsiao-Lung Cheng, Pei-Lin Tien, Chi-Mao Hung, Wen-Pin Liu
  • Patent number: 11386535
    Abstract: The disclosure provides an image blending method. The method includes projecting a first image and a second image onto a projection surface by a first projector and a second projector, respectively, and the first image and the second image overlap each other; and projecting the first control pattern onto the first image, adjusting the first control pattern such that a first control pattern frame matches a boundary of an overlapping area, and thereby identifying a position of a first non-overlapping area in the first image. Additionally, a similar operation is performed by the second projector to identify a second non-overlapping area in the second image. All pixels in the first non-overlapping area and the second non-overlapping area are adjusted such that the black-level brightness of the first non-overlapping area and the second non-overlapping area correspond to the black-level brightness of the overlapping area to obtain better brightness uniformity.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: July 12, 2022
    Assignee: Coretronic Corporation
    Inventors: Jyun-Lin Cian, Chi-Wei Lin, Chien-Chun Peng, Yung-Chiao Liu
  • Publication number: 20220216578
    Abstract: The invention discloses a filter device. The filter device comprises a substrate, at least one transmission conductor, and a reference conductor having a slotted structure. The substrate is provided at a first surface thereof with the transmission conductor, and provided at a second surface thereof with the reference conductor. The slotted structure comprises a frame portion, a slotted portion, and a hollow portion. The slotted portion surrounds the frame portion, and the hollow portion is formed in the frame portion. At least one impedance unit is configured on the frame portion. The equivalent filter circuit of the filter device is formed between the transmission conductor, the slotted structure, the reference conductor, and the impedance unit. Thereby, the equivalent filter circuit absorbs at least one noise at at least one specific frequency by the impedance unit to avoid the noise reflected to affect the transmission quality of signal.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 7, 2022
    Inventors: TZONG-LIN WU, HSU-WEI LIU, CHI-HSUAN CHENG, PO-JUI LI
  • Publication number: 20220216301
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 11270052
    Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia Hao Tu, Hsueh-Chih Chou, Sang Hoo Dhong, Jerry Chang Jui Kao, Chi-Lin Liu, Cheng-Chung Lin, Shang-Chih Hsieh
  • Publication number: 20210389952
    Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Kai-Chi HUANG, Chi-Lin LIU, Wei-Hsiang MA, Shang-Chih HSIEH
  • Patent number: 11152923
    Abstract: A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on at least a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have a first voltage swing or a second voltage swing based on the first output signal and the second output signal. The first voltage swing is different from the second voltage swing.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Lee-Chung Lu, Chang-Yu Wu