Abstract: The present invention provides a circuitry including a clock buffer, a first circuit module, and a second circuit module. The clock buffer is configured to generate a first clock signal and a second clock signal. The first circuit module includes a first frequency divider configured to divide the first clock signal to generate a plurality of first divided clock signals. The second circuit module includes a second frequency divider configured to divide the first clock signal to generate a plurality of second divided clock signals. During the frequency division operation, both the first circuit module and the second circuit module utilize the second clock signal for phase alignment, thereby ensuring that the plurality of first divided clock signals and the plurality of second divided clock signals are phase-aligned.