Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A ranging system includes a pinhole camera, a fisheye camera and a processor. The pinhole camera captures a pinhole image. The fisheye camera captures a fisheye image. The processor performs a undistorting process on the fisheye image to obtain a corresponding undistorted fisheye image, perform a size-converting process on the pinhole image to obtain a corresponding size-converted pinhole image, obtain a transformation relation between a pinhole image plane of the pinhole camera and a fisheye image plane of the fisheye camera, obtain a corresponding point of the corresponding undistorted fisheye image corresponding to a target point of the corresponding size-converted pinhole image based on the transformation relation, and obtain a distance between the ranging system and the physical point based on the transformation relation, the target point and the corresponding point.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: A circuit board device includes a transition region that includes a first conductive layer at a first level, a second conductive layer at a second level, and conductive vias. The first conductive layer includes a pad connected to the solderless connector, a transmission line, and a first reference layer. The transmission line includes first and second segments. A second width of the second segment is the same as or less than a first width of the first segment. The first reference layer has a first anti-pad region for the pad and the transmission line disposed therein. In a plan view, the first anti-pad region surrounding the pad is completely located within a second anti-pad region of a second reference layer of the second conductive layer. The conductive vias are disposed between the first and second conductive layers and surround the pad.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a conductive terminal. The first die includes a first connector, and the second die includes a second connector. The first encapsulant includes: a first portion, on the second die; a second portion, sandwiched between a first sidewall of the first die and a first sidewall of the second die; and a third portion, covering a second sidewall of the second die. The second encapsulant, laterally encapsulating the first die, the second die and the first encapsulant. The conductive terminal, electrically connected to the first die and the second die through a redistribution layer (RDL) structure. The third portion of first encapsulant is sandwiched between the second sidewall of the second die and the second encapsulant.

Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.

Abstract: An antenna module includes a feeding end, multiple first forked radiators, and multiple connecting parts. The first forked radiators are disposed side by side. The connecting parts respectively extend from the feeding end to the first forked radiators. The feeding end, the first forked radiators, and the connecting parts are located on a same plane. The antenna module resonates at a frequency band, and a path length from the feeding end to an end of each of the forked radiators through the corresponding connecting part is ¼ wavelength of the frequency band.

Abstract: A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Abstract: Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a dielectric layer, a source electrode, and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the dielectric layer is disposed on a side of the active layer, and the source electrode and the drain electrode pass through the dielectric layer to electrically connect with the active layer, wherein a first contact surface is formed between the source electrode and the active layer, a second contact surface is formed between the drain electrode and the active layer, the first contact surface and the second contact surface are subjected to a plasma treatment or a deposition treatment to form a protective interface layer.

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Abstract: A palette decoding apparatus includes a palette color storage device which stores palette colors, a color index storage device which stores color indices of pixels, and a palette value processing circuit which generates a palette value for each pixel by reading data from the color index storage device and the palette color storage device. A frame is divided into first coding units, and each first coding unit is sub-divided into one or more second coding units. Before a palette value of a last pixel in a first coding unit is generated by the palette value processing circuit, a palette value of a non-last pixel in the first coding unit is generated by the palette value processing circuit and used by a reconstruction circuit of the video decoder.

Abstract: A palette decoding apparatus includes a palette color storage device which stores palette colors, a color index storage device which stores color indices of pixels, and a palette value processing circuit which generates a palette value for each pixel by reading data from the color index storage device and the palette color storage device. A frame is divided into first coding units, and each first coding unit is sub-divided into one or more second coding units. Before a palette value of a last pixel in a first coding unit is generated by the palette value processing circuit, a palette value of a non-last pixel in the first coding unit is generated by the palette value processing circuit and used by a reconstruction circuit of the video decoder.

Abstract: A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.

Abstract: A method for treating coronavirus infection by administering to a subject in need of the treatment an effective amount of one or more of the following compounds: aklavin, sanguinarine, amiodarone, chlorpromazine, clomiphene, dihydroergotamine, dipyridamole, emetine, ephedrine, prochlorperazine, promazine, propiomazine, aminacrine, fluphenazine, fenoterol, peruvoside, proglumide, atenolol, nerifolin, nefopam, cycloheximide, avermectin B1, bepridil, cinnarizine, ethisterone, pararosaniline, methylbenzethonium, niclosamide, pipobroman, homidium, calcimycin, anisomycin, metergoline, amodiaquine, danazol, danthron, ethopropazine, eucatropine, nortriptyline, resorcinol, mebhydrolin, mebeverine, trimipramine, triflupromazine, chlorprothixene, cyclobenzaprine, enoxacin, sulfanitran, monensin, nigericin, perphenazine, methoxamine, astemizole, trifluoperazine, acriflavinium, rotenone, acebutolol, quabain, methiothepin, convallatoxin, halcinonide, cyclosporin, pimethixene, mycophenolic acid, promethazine, mesoridazine,

Abstract: A method for treating coronavirus infection by administering to a subject in need of the treatment an effective amount of one or more of the following compounds: aklavin, sanguinarine, amiodarone, chlorpromazine, clomiphene, dihydroergotamine, dipyridamole, emetine, ephedrine, prochlorperazine, promazine, propiomazine, aminacrine, fluphenazine, fenoterol, peruvoside, proglumide, atenolol, nerifolin, nefopam, cycloheximide, avermectin B1, bepridil, cinnarizine, ethisterone, pararosaniline, methylbenzethonium, niclosamide, pipobroman, homidium, calcimycin, anisomycin, metergoline, amodiaquine, danazol, danthron, ethopropazine, eucatropine, nortriptyline, resorcinol, mebhydrolin, mebeverine, trimipramine, triflupromazine, chlorprothixene, cyclobenzaprine, enoxacin, sulfanitran, monensin, nigericin, perphenazine, methoxamine, astemizole, trifluoperazine, acriflavinium, rotenone, acebutolol, quabain, methiothepin, convallatoxin, halcinonide, cyclosporin, pimethixene, mycophenolic acid, promethazine, mesoridazine,

Abstract: The present invention provides a method of synthesizing a target polynucleotide encoding a protein, which uses a primer extension technique to constitute the target polynucleotide sequence. Preferably, the method is applied in a method for highly expressing a protein encoded by the target polynucleotide in a host.

Abstract: The present invention relates to an organic electroluminescent device with a light-emitting layer, the light-emitting layer comprising a photo-crosslinkable conductive polymeric host material suitable for facilitating full-color display by spin coating; and at least one small-molecule light-emitting material to achieve high power efficiency. The color-purity of device of the present invention is independent of the distribution of molecular weight of the polymer in the light-emitting layer.