Patents by Inventor Chi Min-Hwa

Chi Min-Hwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8860155
    Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Chi Min-Hwa, Mieno Fumitake
  • Publication number: 20130099336
    Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.
    Type: Application
    Filed: March 22, 2012
    Publication date: April 25, 2013
    Applicant: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Chi Min-Hwa, Mieno Fumitake
  • Patent number: 7602006
    Abstract: A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using lower voltages and increasing the miniaturization of the device. The floating gate may be used in n-type and p-type devices, including n-type and p-type fin-FET devices. The stored charge may be electrons or holes.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: October 13, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chao Huang, Chi Min-Hwa, Fu-Liang Yang
  • Publication number: 20060237770
    Abstract: A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using lower voltages and increasing the miniaturization of the device. The floating gate may be used in n-type and p-type devices, including n-type and p-type fin-FET devices. The stored charge may be electrons or holes.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 26, 2006
    Inventors: Chien-Chao Huang, Chi Min-Hwa, Fu-Liang Yang