Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.

Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.

Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.

Abstract: A method for configuring a via in a semiconductor device includes determining time dependent dielectric breakdown failure rate as a function of distance between the via and a metal line, generating candidate via configurations with different sizes, rotation, and offset values for the via, determining TDDB failure rate for the candidate via configurations, and selecting one of the candidate via configurations with an optimal TDDB failure rate for the via.

Abstract: A method for configuring a via in a semiconductor device includes determining time dependent dielectric breakdown failure rate as a function of distance between the via and a metal line, generating candidate via configurations with different sizes, rotation, and offset values for the via, determining TDDB failure rate for the candidate via configurations, and selecting one of the candidate via configurations with an optimal TDDB failure rate for the via.

Abstract: A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device.

Abstract: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.

Abstract: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.

Abstract: A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.

Abstract: A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.

Abstract: A method of determining quantitatively the exposure levels for photoresists in semiconductor photolithography employs a specially designed grating pattern on a mask. The mask is first used to expose a series of LIM image gratings of different dosages. Then a normal plane wave at a longer wavelength is incident on these gratings one by one, and some nonzero order diffraction efficiency of the grating is measured to determine quantitatively the correct dosage to be used. This method can make a determination of exposure dosage, without knowledge of underlying film thickness and refractive index, and handle either resist thickness change or underlying film thickness/refractive index change or both.

Abstract: A method of determining quantitatively the exposure levels for photoresists in semiconductor photolithography employs a specially designed grating pattern on a mask. The mask is first used to expose a series of LIM image gratings of different dosages. Then a normal plane wave at a longer wavelength is incident on these gratings one by one, and some nonzero order diffraction efficiency of the grating is measured to determine quantitatively the correct dosage to be used. This method can make a determination of exposure dosage, without knowledge of underlying film thickness and refractive index, and handle either resist thickness change or underlying film thickness/refractive index change or both.

Abstract: A simplified method of forming a phase shift structure for a lithographic mask includes the conformal deposition of a phase shift material, preferably having an index of refraction similar to that of the mask substrate, over a patterned layer of opaque material and exposed areas of the mask substrate corresponding to the pattern. The thickness of the opaque patterned layer, in combination with the conformal deposition preferably establishes a differentially altered optical path length to produce a phase shift which enhances contrast and increases illumination and resolution in fine patterns. In variant forms of the invention, the conformal deposition of either phase shift material or a sidewall spacer material is followed by an anisotropic removal of material to form the phase shift structure.

Abstract: A method of determining quantitatively the exposure levels for photoresists in semiconductor photolithography employs a specially designed grating pattern on a mask. The mask is first used to expose a series of LIM image gratings of different dosages. Then a normal plane wave at a longer wavelength is incident on these gratings one by one, and some nonzero order diffraction efficiency of the grating is measured to determine quantitatively the correct dosage to be used. This method can make a determination of exposure dosage, without knowledge of underlying film thickness and refractive index, and handle either resist thickness change or underlying film thickness/refractive index change or both.

Abstract: A subtractive method for making a Levenson type lithographic phase shift mask using a sacrificial etch monitor film in which some of the monitor film is left standing on the opaque portions of the mask. The monitor film otherwise is consumed when it is simultaneously etched with selected portions of the mask substrate to produce recesses of desired depth in the substrate. The etching is stopped upon detecting that the etched monitor film is completely consumed. The technique also is adapted for the fabrication of a RIM type lithographic phase shift mask combined with the Levenson type phase shift mask in the same mask. The technique further is adapted to include 90 degree shift transitions at the end of the Levenson line-space pairs of the mask. The monitor film left standing on the opaque portions of the mask provides self-aligned phase error correction to offset sidewall scattering in the Levenson type mask.