Abstract: A method and system for audibly outputting text messages includes: setting a vocalizing function for audibly outputting text messages, searching a character speech library for each character of a received text message, and acquiring pronunciation data of each character of the received text message. The method and the system further includes vocalizing the pronunciation data of each character of the received text message, generating a voice message, and audibly outputting the generated voice message.

Abstract: A method and system for audibly outputting text messages includes: setting a vocalizing function for audibly outputting text messages, searching a character speech library for each character of a received text message, and acquiring pronunciation data of each character of the received text message. The method and the system further includes vocalizing the pronunciation data of each character of the received text message, generating a voice message, and audibly outputting the generated voice message.

Abstract: A switching regulator automatically operates in pulse width modulation (“PWM”) mode for high load currents and in burst mode for low load currents. The switching regulator includes a pair of switches to provide a regulated current to a load. The switching regulator further includes a multi-input comparator. A first input of the comparator is coupled to an output of the pair of switches. A second input of the comparator is coupled to a filtered version of the output and a third input is coupled to a reference waveform. The first, second and third inputs of the comparator form a combined input signal to the comparator. An output signal of the comparator is generated by comparing the combined input signal to a threshold of the comparator. The output signal determines a switching frequency of the pair of switches such that the switching frequency is automatically reduced when the load is decreased.

Abstract: A switching regulator automatically operates in pulse width modulation (“PWM”) mode for high load currents and in burst mode for low load currents. The switching regulator includes a pair of switches to provide a regulated current to a load. The switching regulator further includes a multi-input comparator. A first input of the comparator is coupled to an output of the pair of switches. A second input of the comparator is coupled to a filtered version of the output and a third input is coupled to a reference waveform. The first, second and third inputs of the comparator form a combined input signal to the comparator. An output signal of the comparator is generated by comparing the combined input signal to a threshold of the comparator. The output signal determines a switching frequency of the pair of switches such that the switching frequency is automatically reduced when the load is decreased.

Abstract: A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal, receives a second pulse signal indicative that the phase of the input signal lags that of the reference signal, and generates a state signal indicative of whether the first pulse signal is ahead of the second pulse signal. A pulse-width detector generates a first width signal indicative of into which range the width of the first pulse signal falls; another pulse-width detector generates a second width signal indicative of into which range the width of the second pulse signal falls. According to the state signal and the first and the second width signals, control logic generates a regulation signal for use in adjusting the frequency of the input signal.

Abstract: A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal, receives a second pulse signal indicative that the phase of the input signal lags that of the reference signal, and generates a state signal indicative of whether the first pulse signal is ahead of the second pulse signal. A pulse-width detector generates a first width signal indicative of into which range the width of the first pulse signal falls; another pulse-width detector generates a second width signal indicative of into which range the width of the second pulse signal falls. According to the state signal and the first and the second width signals, control logic generates a regulation signal for use in adjusting the frequency of the input signal.

Abstract: A low noise voltage regulator circuit with fast stable output voltage is disclosed. The low noise voltage regulator circuit contains a reference voltage generator, for generating a reference voltage; a switching circuit, which is electrically coupled to the output of reference voltage generator and has two states; and a stabilizing circuit. When the switching circuit is at a first state, the reference voltage is coupled to the stabilizing circuit without being filtered; when the switching circuit is at a second state, the reference voltage is filtered by a low pass filter before being coupled to the stabilizing circuit. A switching control signal is used to switch the switching circuit between the two states. The filtered reference voltage is used to generate a low noise regulated output voltage.

Abstract: A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.

Abstract: A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.

Abstract: A low noise voltage regulator circuit with fast stable output voltage is disclosed. The low noise voltage regulator circuit contains a reference voltage generator, for generating a reference voltage; a switching circuit, which is electrically coupled to the output of reference voltage generator and has two states; and a stabilizing circuit. When the switching circuit is at a first state, the reference voltage is coupled to the stabilizing circuit without being filtered; when the switching circuit is at a second state, the reference voltage is filtered by a low pass filter before being coupled to the stabilizing circuit. A switching control signal is used to switch the switching circuit between the two states. The filtered reference voltage is used to generate a low noise regulated output voltage.

Abstract: A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in an order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect. The subthreshold and leakage currents passing through the largest switch elements are blocked by the use of an additional switch element to isolate the largest switch element.

Abstract: A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. When the phase-locked loop circuit starts, the control unit causes a detection output signal from the dual-mode phase/frequency detector to correspond to a digital signal from the digital phase/frequency detector. When the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to an analog signal from the analog phase/frequency detector. The phase-locked loop with dual-mode phase/frequency detection has the advantages of providing linear characteristics, fast switching speed, and high sensitivity.

Abstract: A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. When the phase-locked loop circuit starts, the control unit causes a detection output signal from the dual-mode phase/frequency detector to correspond to a digital signal from the digital phase/frequency detector. When the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to an analog signal from the analog phase/frequency detector. The phase-locked loop with dual-mode phase/frequency detection has the advantages of providing linear characteristics, fast switching speed, and high sensitivity.