Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: Embodiments described herein relate to methods of printing double exposure patterns in a lithography environment. The methods include determining a second exposure pattern to be exposed with a first exposure pattern in a lithography process. The second exposure pattern is determined with a rule-based process flow or a lithography model process flow.

Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.

Abstract: A light emitting diode is provided. The light emitting diode includes: a semiconductor stack, including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a first insulating layer, formed on the semiconductor stack; a reflective electrode layer, partially formed on the first insulating layer, wherein a minimum distance between an edge of the reflective electrode layer and the semiconductor stack is a fourth distance, and the fourth distance is in a range of 1 ?m to 5 ?m; and a fourth insulating layer, formed on the reflective electrode layer, wherein the fourth insulating layer is aluminum oxide.

Abstract: A dual circularly polarized antenna array includes an insulating substrate, an M number of feed modules, and an M number of antenna groups. The insulating substrate includes an M number of preset points. The M antenna groups are respectively disposed on the M preset points, and each antenna group includes four antennas. Any two opposite ones of the four antennas jointly have a 180-degree rotational symmetry relative to a corresponding one of the M preset points. Each antenna includes a conductive sheet, and a first feed point and a second feed point that are electrically coupled to one of the M feed modules. The first feed points of the four antennas can jointly generate a left-hand circular polarization through one of the M feed modules, and the second feed points of the four antennas can jointly generate a right-hand circular polarization through one of the M feed modules.

Abstract: A projection device includes a shell, an illumination system, an electrical connecting element, a light valve system, and a projection lens. The illumination system is disposed in the shell and provides an illumination beam. The light valve system includes a dustproof module and a light valve module. The dustproof module includes a frame and two transparent plates. An accommodation space is formed by the frame and the two transparent plates. The light valve module includes a light valve and an electrical connecting part. The light valve and the two transparent plates are located on a transmission path of the illumination beam, and the light valve converts the illumination beam into an image beam. One end of the electrical connecting part located in the accommodation space is electrically connected to the light valve, and the other end located outside the accommodation space is detachably electrically connected to the electrical connecting element.

Abstract: Described herein are platinum(II) complexes and their methods of making and using thereof. The design of the platinum(II) complexes results in emission in the blue spectral region with high quantum yields and fast radiative decay rates at room temperature. The platinum(II) complexes can be used to fabricate efficient blue emitting OLEDs.

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.

Abstract: A device may receive a PDCCH signal, may decode encoded bits of the PDCCH signal to generate coded bits, may reencode the coded bits, and may calculate a detection error probability of each coded bit at an output of soft demodulation. The device may calculate a channel decoding error probability that cyclic redundancy check bits are still attached to the coded bits, and may calculate an error probability of channel reencoding, of each coded bit, due to error propagation of polar decoding and reencoding. The device may calculate a probability density of a BMR associated with the coded bits, and may calculate a threshold based on the detection error probability, the channel decoding error probability, the error probability of channel reencoding, and the probability density of a BMR. The device may determine that the PDCCH signal is invalid based on the BMR being greater than the threshold.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: A method includes receiving a three-dimensional (3D) avatar. The method further includes generating two-dimensional (2D) images of the 3D avatar from different angles that surround the 3D avatar. The method further includes providing the 2D images as input to a trained machine-learning model. The method further includes generating, with the machine-learning model, a concatenated embedding of the 2D images. The method further includes analyzing, with the machine-learning model based on the concatenated embedding, at least one attribute associated with the 3D avatar, wherein the at least one attribute is selected from a group of a shape of the 3D avatar, an outfit on the 3D avatar, and combinations thereof. The method further includes outputting, with the machine-learning model, a determination that the at least one attribute of the 3D avatar is abusive.

Abstract: Disclosed are a semiconductor epitaxial structure, a preparation method thereof, and a light-emitting diode. The semiconductor epitaxial structure includes a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer that are sequentially arranged on a substrate. The material of the buffer layer is AlxInyGa(1-x-y)N, wherein 0x and 0?y. The buffer layer is doped with carbon impurities. The doping concentration of the carbon impurities in the buffer layer is lower than 9E17 atoms/cm3. The present invention grows the buffer layer using a high-temperature growth method. The buffer layer has a lower defect density and a lower content of carbon impurities, making it more possible to facilitate enhancement of the lattice quality of the subsequent epitaxial structure and improve the luminous efficiency and anti-aging capability of the light-emitting diode.

Abstract: A method for forming a photomask includes following operations. A first photomask is received. The first photomask includes a first pattern and a first scattering bar. The first photomask is used to remove a first portion of a target layer to form a first opening and a second opening. The first opening corresponds to the first pattern, and the second opening corresponds to the first scattering bar. A second photomask is received. The second photomask includes a second pattern. The second photomask is used to remove a second portion of the target layer to form a third opening. The third opening corresponds to the second pattern. The second opening is widened to form the third opening using the second photomask.

Abstract: A dual circularly polarized antenna array includes an insulating substrate, an M number of feed modules, and an M number of antenna groups. The insulating substrate includes an M number of preset points. The M antenna groups are respectively disposed on the M preset points, and each antenna group includes four antennas. Any two opposite ones of the four antennas jointly have a 180-degree rotational symmetry relative to a corresponding one of the M preset points. Each antenna includes a conductive sheet, and a first feed point and a second feed point that are electrically coupled to one of the M feed modules. The first feed points of the four antennas can jointly generate a left-hand circular polarization through one of the M feed modules, and the second feed points of the four antennas can jointly generate a right-hand circular polarization through one of the M feed modules.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Abstract: Depositing gallium nitride and carbon (GaN:C) (e.g., in the form of composite layers) when forming a gallium nitride drain of a transistor provides a buffer between the gallium nitride of the drain and silicon of a substrate in which the drain is formed. As a result, gaps and other defects caused by lattice mismatch are reduced, which improves electrical performance of the drain. Additionally, current leakage into the substrate is reduced, which further improves electrical performance of the drain. Additionally, or alternatively, implanting silicon in an aluminum nitride (AlN) liner for a gallium nitride drain reduces contact resistance at an interface between the gallium nitride and the silicon. As a result, electrical performance of the transistor is improved.

Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-layers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N stack, where 0<x1?1 and 0?y1<1. An LED device including the multi-quantum well structure is also disclosed.

Abstract: A semiconductor package structure includes a control unit and a memory unit. The control unit includes a first wafer and a second wafer that are vertically stacked. The memory unit is disposed on the second wafer of the control unit. The memory unit includes multiple third wafers and a fourth wafer that are stacked vertically. The memory unit overlaps the control unit in a normal direction of the semiconductor package structure. In addition, a manufacturing method of the semiconductor package structure is provided.

Abstract: A directional position system for use in facilities having rooms, hallways, and other areas can include a plurality of portable units carried or worn by selected users in the facility; a plurality of stationary units mounted in each of a number of locations within the facility; and an administrative unit. At least one of the portable units can include at least one button for sending a signal, when pressed, for a type of emergency. At least one of the stationary units can include a display for indicating a direction to move during an emergency. The administrative unit can be configured to be monitored by security personnel and can be configured to receive any signal transmitted from any of the plurality of portable units or any of the plurality of stationary units. The plurality of portable units, the plurality of stationary units, and the administrative unit can form a mesh network.

Abstract: A lithography method to pattern a first semiconductor wafer is disclosed. An optical mask is positioned over the first semiconductor wafer. A first region of the first semiconductor wafer is patterned by directing light from a light source through transparent regions of the optical mask. A second region of the first semiconductor wafer is patterned by directing energy from an energy source to the second region, wherein the patterning of the second region comprises direct-beam writing.