Patents by Inventor Chi-Ming Tsai

Chi-Ming Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151464
    Abstract: An LED and a light emitting device are provided, which includes an epitaxial structure, a transparent conductive layer, an insulating structure and a metal reflective layer. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer. The transparent conductive layer is disposed on the second semiconductor layer. The insulating structure is disposed on the transparent conductive layer, and an opening is defined in the insulating structure. The transparent conductive layer is exposed from the opening. A step portion is formed on a sidewall of the opening, and divides the opening into a first opening and a second opening. An opening width of the first opening is smaller than that of the second opening. The metal reflective layer is disposed on the insulating structure. The metal reflective layer fills the first opening and the second opening, and forms electrical contact with the second semiconductor layer.
    Type: Application
    Filed: November 5, 2024
    Publication date: May 8, 2025
    Inventors: XIUSHAN ZHU, YAN LI, QI JING, Zhihao BAO, Qingchao YANG, Chunhsien LEE, Chi-Ming TSAI, Juchin TU, Chung-Ying CHANG
  • Patent number: 12293969
    Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 6, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Patent number: 12288729
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: February 7, 2024
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20250120222
    Abstract: A light-emitting device includes a semiconductor epitaxial structure including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked in such order in a stacking direction, and including a plurality of through holes. The through holes extend downwardly in a direction from the second semiconductor layer to the first semiconductor layer. The through holes expose a portion of a surface of the first semiconductor layer. The light-emitting device has an ampacity. Each of the through holes has a first radius. A ratio of the first radius to the ampacity ranges from 0.1 to 0.4. A light-emitting apparatus including the light-emitting device is also provided.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Inventors: Sihe CHEN, Yashu ZANG, Weichun TSENG, Shaohua HUANG, Chi -Ming TSAI, Chung-ying CHANG, Su-Hui LIN, Siyi LONG
  • Patent number: 12254258
    Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Publication number: 20250068082
    Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.
    Type: Application
    Filed: November 11, 2024
    Publication date: February 27, 2025
    Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU
  • Publication number: 20250028251
    Abstract: A method is provided including directing a plurality of beams of radiation at a first area of a first layer on a substrate, each beam incident upon a different portion of a plurality of portions within the first area. Each portion has an area of a first size, the plurality of beams of radiation are directed at the first area based on a first pattern, the first pattern comprises a plurality of unit cells that include a plurality of on cells and a plurality of off cells, each unit cell has an area smaller than the first size, the plurality of on cells identify locations within the first area at which a beam of radiation of the plurality of beams of radiation is centrally focused, and the plurality of off cells identify locations within the first area at which no beam of radiation of the plurality of beams of radiation is centrally focused.
    Type: Application
    Filed: November 9, 2022
    Publication date: January 23, 2025
    Inventors: Thomas L. LAIDIG, Chi-Ming TSAI
  • Patent number: 12174529
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations. A first layout including a plurality of first features is provided. A modified second layout is determined. The modified second layout includes a plurality of modified features separated from each other, and each of the plurality of modified features respectively overlaps each of the plurality of first features. The modified second layout is outputted to a photomask.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Chung Hu, Chi-Ta Lu, Chi-Ming Tsai
  • Publication number: 20240386176
    Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Patent number: 12140871
    Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: November 12, 2024
    Assignee: Applied Materials, Inc.
    Inventors: YingChiao Wang, Chi-Ming Tsai, Chun-chih Chuang, Yung Peng Hu
  • Publication number: 20240312939
    Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.
    Type: Application
    Filed: May 27, 2024
    Publication date: September 19, 2024
    Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
  • Publication number: 20240280913
    Abstract: Embodiments of the present disclosure relate to methods, systems and apparatus for improving dose uniformity of the photolithography system. The method includes projecting a write beam from a projection unit toward a mask to form a plurality of incident lights, adjusting the projection unit to create a distribution of incidence angles corresponding to the incident lights, focusing the plurality of incident lights toward a photoresist layer disposed over a substrate with a lens, removing portions of the photoresist layer to form the device pattern, and forming structures on the substrate corresponding to the device pattern. The mask has a mask pattern corresponding to a device pattern. By focusing the plurality of incident lights towards the photoresist, a swing curve of the incident lights interfere to reduce a total swing curve of the incident lights to develop a photoresist layer with a photoresist pattern corresponding to the device pattern.
    Type: Application
    Filed: February 20, 2023
    Publication date: August 22, 2024
    Inventor: Chi-Ming TSAI
  • Publication number: 20240280911
    Abstract: A digital lithography system includes scan regions including a first scan region and a second scan region adjacent to the first scan region. The digital lithography system further includes exposure units located above the scan regions, a memory, and at least one processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with the first scan region and a second exposure unit associated with the second scan region. The processing device is to perform operations including initiating a digital lithography process to pattern a substrate disposed on the stage in accordance with instructions, and performing exposure unit boundary smoothing with respect to the first and second exposure units during the digital lithography process.
    Type: Application
    Filed: June 14, 2021
    Publication date: August 22, 2024
    Inventors: CHI-MING TSAI, THOMAS L. LAIDIG, DOUGLAS VAN DEN BROEKE
  • Publication number: 20240248046
    Abstract: Implementations disclosed describe, among other things, a system and a method of using a wafer inspection system that includes a plurality of inspection heads configured to concurrently inspect a separate region of a plurality of regions of a wafer. Each inspection head includes an illumination subsystem to illuminate a corresponding region of the wafer, a collection subsystem to collect a portion of light reflected/scattered from the corresponding region of the wafer. Each inspection head further includes a light detection subsystem to detect the collected light and generate one or more signals representative of a state of the corresponding region of the wafer. The wafer inspection system further includes a processing device configured to determine, using the one or more signals received from each of the inspection heads, the quality of the wafer.
    Type: Application
    Filed: January 5, 2024
    Publication date: July 25, 2024
    Inventors: Keith Wells, Ron Naftali, Elad Eizner, Tal Kuzniz, Chi-Ming Tsai
  • Publication number: 20240231239
    Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.
    Type: Application
    Filed: October 21, 2022
    Publication date: July 11, 2024
    Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU
  • Patent number: 12021169
    Abstract: The disclosure illustrates a composite substrate and a method for manufacturing the same, the method including: disposing a mask layer on an upper surface of a substrate; forming a plurality of mask patterns spaced apart from each other to form a plurality of intervals thereamong; filling a dummy metallic material into the intervals; removing the mask patterns to form a mesh-like dummy metallic layer; and removing the dummy metallic layer while depositing a nitride layer so as to form a mesh-like structure confined by the nitride layer and the substrate. The disclosure also illustrates a method for manufacturing a light-emitting device using the composite substrate.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: June 25, 2024
    Assignee: Anhui Sanan Optoelectronics Co., Ltd.
    Inventors: Yu Wang, Chiahao Tsai, Qin Wang, Bin Fang, Liangliang Gui, Jinkuang Dong, Shan Wang, Zhaoming Huang, Chih-Chung Chiu, Chi-ming Tsai
  • Patent number: 12021050
    Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Ho Tsai, Jyun-Hong Chen, Chun-Chen Liu, Yu-Nu Hsu, Peng-Ren Chen, Wen-Hao Cheng, Chi-Ming Tsai
  • Publication number: 20240178091
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20240143887
    Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones; and adjusting line widths in the compensation zones of the feature according to the compensation values associated with the respective compensation zones.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: CHI-TA LU, CHIA-HUI LIAO, YIHUNG LIN, CHI-MING TSAI
  • Publication number: 20240145632
    Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG