Patents by Inventor Chi-Ming Yeung
Chi-Ming Yeung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907139Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: GrantFiled: December 20, 2022Date of Patent: February 20, 2024Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Publication number: 20240045813Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).Type: ApplicationFiled: August 21, 2023Publication date: February 8, 2024Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Patent number: 11768780Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).Type: GrantFiled: March 31, 2022Date of Patent: September 26, 2023Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Publication number: 20230236997Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: ApplicationFiled: December 20, 2022Publication date: July 27, 2023Inventors: Chi-Ming YEUNG, Yoshie NAKABAYASHI, Thomas GIOVANNINI, Henry STRACOVSKY
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Patent number: 11537540Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: GrantFiled: May 10, 2021Date of Patent: December 27, 2022Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Publication number: 20220334981Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).Type: ApplicationFiled: March 31, 2022Publication date: October 20, 2022Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Patent number: 11294830Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).Type: GrantFiled: April 1, 2020Date of Patent: April 5, 2022Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Publication number: 20210326279Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: ApplicationFiled: May 10, 2021Publication date: October 21, 2021Inventors: Chi-Ming YEUNG, Yoshie NAKABAYASHI, Thomas GIOVANNINI, Henry STRACOVSKY
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Patent number: 11003601Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: GrantFiled: April 1, 2020Date of Patent: May 11, 2021Assignee: Rambus, Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Publication number: 20200293468Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: ApplicationFiled: April 1, 2020Publication date: September 17, 2020Inventors: Chi-Ming YEUNG, Yoshie NAKABAYASHI, Thomas GIOVANNINI, Henry STRACOVSKY
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Publication number: 20200293461Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).Type: ApplicationFiled: April 1, 2020Publication date: September 17, 2020Inventors: Chi-Ming YEUNG, Yoshie NAKABAYASHI, Thomas GIOVANNINI, Henry STRACOVSKY
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Patent number: 10613995Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).Type: GrantFiled: March 15, 2016Date of Patent: April 7, 2020Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Patent number: 10614002Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: GrantFiled: December 31, 2018Date of Patent: April 7, 2020Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Publication number: 20190251044Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: ApplicationFiled: December 31, 2018Publication date: August 15, 2019Inventors: Chi-Ming YEUNG, Yoshie NAKABAYASHI, Thomas GIOVANNINI, Henry STRACOVSKY
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Patent number: 10255220Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.Type: GrantFiled: February 23, 2016Date of Patent: April 9, 2019Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, David Secker, Ravindranath Kollipara, Shajith Musaliar Sirajudeen, Yoshie Nakabayashi
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Patent number: 10169258Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: GrantFiled: March 15, 2016Date of Patent: January 1, 2019Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Patent number: 9921751Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.Type: GrantFiled: January 19, 2016Date of Patent: March 20, 2018Assignee: Rambus Inc.Inventors: Richard E. Perego, Pradeep Batra, Steven Woo, Lawrence Lai, Chi-Ming Yeung
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Patent number: 9880971Abstract: A memory appliance system is described and includes a processor coupled to one or more communication channels with a command interface, wherein the processor is configured for communicating commands over the communication channels. A plurality of Smart Memory Cubes (SMCs) is coupled to the processor through the communication channels. Each of the SMCs includes a controller that is programmable, and a plurality of memory devices. The controller is configured to respond to commands from the command interface to access content stored in one or more of the plurality of memory devices and to perform data operations on content accessed from the plurality of memory devices.Type: GrantFiled: November 12, 2014Date of Patent: January 30, 2018Assignee: Rambus Inc.Inventors: Keith Lowery, Vlad Fruchter, Chi-Ming Yeung
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Patent number: 9841791Abstract: A rack unit configuration is described that includes a first printed circuit board (PCB) assembly interleaved with a second PCB assembly that is inverted with respect to the first PCB assembly. The configuration of the first PCB assembly and the second PCB assembly allow for increased component and power densities within computing systems, memory systems, etc. The increased density may be achieved while allowing sufficient mechanical clearance to allow easy component replacement and servicing (e.g., and hot pluggability). Power density may also be increased with PCB assemblies including nested and interleaved power modules.Type: GrantFiled: December 12, 2014Date of Patent: December 12, 2017Assignee: Rambus Inc.Inventors: Donald R. Mullen, Chi-Ming Yeung, David A. Secker
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Patent number: 9824779Abstract: In response to a first memory access transaction having a first base address, data fields and a repair fields are retrieved from a first DRAM channel. The data fields include a first data field. The repair fields include a first repair field storing repair data. The repair data is to replace any data in the first data field. In response to a second memory access transaction having a second base address, repair tag fields are retrieved from a second DRAM channel. The repair tag fields include a repair tag field that indicates the repair data is be replace the data stored in the first data field.Type: GrantFiled: May 20, 2015Date of Patent: November 21, 2017Assignee: Rambus Inc.Inventors: Frederick A. Ware, Vlad Fruchter, Chi-Ming Yeung