Patents by Inventor Chi-Ming Yu

Chi-Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984486
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Publication number: 20240103209
    Abstract: The present disclosure relates to an optical filter and a method of producing the same. In the producing method, a thermal evaporation deposition process of a sacrificial layer, and depositions process of a base layer and a dielectric stack layer are sequentially performed on a substrate having a trench with a specific width, so that the base layer and the dielectric stack layer extend outward to form a solidified structure with a specific length. Next, a fixed layer is affixed to the dielectric stack layer, and the sacrificial layer is removed using a solvent to remove the substrate. As such, structural strength and flatness of the produced optical filter are enhanced, and a volume thereof is reduced, such that the optical filter can be applied to automated processes of miniaturized elements.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 28, 2024
    Inventors: Chi-Ming YU, Zong Han LI, Chin-Pin YEH
  • Patent number: 11941338
    Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yi Hu, Chih-Ming Chao, Chi-Yeh Yu
  • Publication number: 20240088285
    Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Kuei-Ming Chen, Chi-Ming Chen, Chung-Yi Yu
  • Patent number: 11923237
    Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Fan
    Patent number: 8360719
    Abstract: A fan includes an impeller comprising a hub and a plurality of blades, and a housing receiving the impeller and comprising a first frame having a side wall and an inlet, and a second frame having a side wall and an outlet, wherein an inner surface on a periphery of the inlet is a smooth curved surface. The first or second frame has at least one side hole disposed at the side wall of the first or second frame.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: January 29, 2013
    Assignee: Delta Electronics, Inc.
    Inventors: Jing-Cao Huang, Chui Chu, Yi-Liang Gong, Chi-Ming Yu
  • FAN
    Publication number: 20100183437
    Abstract: A fan includes an impeller comprising a hub and a plurality of blades, and a housing receiving the impeller and comprising a first frame having a side wall and an inlet, and a second frame having a side wall and an outlet, wherein an inner surface on a periphery of the inlet is a smooth curved surface. The first or second frame has at least one side hole disposed at the side wall of the first or second frame.
    Type: Application
    Filed: October 14, 2009
    Publication date: July 22, 2010
    Inventors: Jing-Cao HUANG, Chui CHU, Yi-Liang GONG, Chi-Ming YU
  • Patent number: 6700260
    Abstract: A rotor structure of a motor is provided. The rotor structure includes a magnet having a first annular wall, a magnet holder having a base and a second annular wall connected with the first annular wall of the magnet for fixing the magnet, a shaft having one end mounted through the base of the magnet holder, and a stopper mounted in the other end of the shaft.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: March 2, 2004
    Assignee: Delta Electronics, Inc.
    Inventors: Kuotung Hsu, Chih-Chang Chen, Chi-Ming Yu
  • Publication number: 20020008433
    Abstract: A rotor structure of a motor is provided. The rotor structure includes a magnet having a first annular wall, a magnet holder having a base and a second annular wall connected with the first annular wall of the magnet for fixing the magnet, a shaft having one end mounted through the base of the magnet holder, and a stopper mounted in the other end of the shaft.
    Type: Application
    Filed: December 19, 2000
    Publication date: January 24, 2002
    Applicant: Delta Electronics, Inc.
    Inventors: Kuotung Hsu, Chih-Chang Chen, Chi-Ming Yu