Abstract: Provided are techniques for verifying application compatibility, comprising providing a configuration knowledge server (CKS) to store information about configuration issues; detecting, by a configuration checking agent (CCA), a reconfiguration of a computing system; signaling, by the CCA, a configuration checking service (CCS), in response to the detecting; in response to the signaling, requesting, by the CCS, a compatibility report, from the CKS, about potential configuration issues with respect to the reconfiguration; transmitting the compatibility report from the CKS to the CCS; parsing, by the CCS, the compatibility report to identify a compatibility issue with respect to the reconfiguration; and in response to identifying the compatibility issue, dynamically performing an action to mitigate the compatibility issue.

Abstract: Provided are techniques for verifying application compatibility, comprising providing a configuration knowledge server (CKS) to store information about configuration issues; detecting, by a configuration checking agent (CCA), a reconfiguration of a computing system; signaling, by the CCA, a configuration checking service (CCS), in response to the detecting; in response to the signaling, requesting, by the CCS, a compatibility report, from the CKS, about potential configuration issues with respect to the reconfiguration; transmitting the compatibility report from the CKS to the CCS; parsing, by the CCS, the compatibility report to identify a compatibility issue with respect to the reconfiguration; and in response to identifying the compatibility issue, dynamically performing an action to mitigate the compatibility issue.

Abstract: A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data storage node of a plurality of data storage nodes by latching data at the first node using the reference input signal; and maintaining a state of a second data storage node of the plurality of data storage nodes by latching data at the second data storage node using the delayed input signal. A circuit for preventing an unintentional state change in a data storage node of a latch is also disclosed.

Abstract: A programmable logic device, in accordance with an embodiment of the present invention, includes a plurality of multiplexers, having fuse input terminals and input signal terminals, and a plurality of associated fuses providing fuse signals to the fuse input terminals to control selection of the input signal terminals. The fuses in a first state select a first input signal terminal of the input signal terminals, with a first multiplexer from the plurality of multiplexers receiving a first logic level signal at the first input signal terminal and providing the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers. The fuses associated with the first set are adapted to be programmed before the fuses associated with the first multiplexer.