Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.

Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: Methods for application management in an electronic device are provided. It is first determined whether the application to be installed is listed in a first list, wherein the first list lists a set of applications which are hardware accelerable. The application is then marked as a hardware accelerable application in response to the application being listed in the first list. Thereafter, the application is installed, wherein a hardware acceleration function of the application is enabled to activate a hardware acceleration unit of the electronic device for hardware acceleration during executing the application being marked as the hardware accelerable application.

Abstract: A light-emitting element includes a light-emitting stacked layer including an upper surface, wherein the upper surface includes a first flat region; a protective layer including a current blocking region on the first flat region; and a cap region on the upper surface, wherein the current blocking region is spatially separate from the cap region; and a first electrode covering the current blocking region.

Abstract: Methods for application management in an electronic device are provided. It is first determined whether the application to be installed is listed in a first list, wherein the first list lists a set of applications which are hardware accelerable. The application is then marked as a hardware accelerable application in response to the application being listed in the first list. Thereafter, the application is installed, wherein a hardware acceleration function of the application is enabled to activate a hardware acceleration unit of the electronic device for hardware acceleration during executing the application being marked as the hardware accelerable application.

Abstract: The present invention relates to a strain of Escherichia coli (E. coli M2H) for biosynthesis of high yield carotenoids, the steps for obtaining E. coli M2H comprises: purifying the host strain JCL1613 for pCW9/P2IDI; create plasmids for producing carotenoid genes; transform the plasmids into JCL1613; utilizing physical method (UV) to induce and improve JCL1613; select the portions with 99% death rate; utilizing 50 mL shake flask incubation; and go through UV screening to obtain the mutated strain of E. coli M2H.