Patents by Inventor Chi-Nan Lin

Chi-Nan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734489
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
  • Publication number: 20200098883
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 26, 2020
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Publication number: 20200044035
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.
    Type: Application
    Filed: November 2, 2018
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
  • Patent number: 10522640
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Patent number: 10345373
    Abstract: A method for inspecting a semiconductor device structure is provided. The method includes receiving a semiconductor device structure having a to-be-inspected feature. The semiconductor device structure has a first surface and a second surface. The method also includes applying a polymer-containing solution over the first surface of the semiconductor device structure. The method further includes disposing a transparent substrate over the first surface of the semiconductor device structure and the polymer-containing solution. In addition, the method includes irradiating the polymer-containing solution with a light to form an adhesive layer between the transparent substrate and the semiconductor device structure. The adhesive layer bonds the transparent substrate and the semiconductor device structure. The method also includes inspecting the to-be-inspected feature.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Baohua Niu, Chia-Nan Ke, Chi-Chun Lin
  • Publication number: 20190187529
    Abstract: A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 20, 2019
    Inventors: SHUO-HONG WANG, Chun-Nan Lin, Chia-Tsung Wu, Chi-Ting Kuo, Ko-Jui Lee, Chia-Hung Li, Chia-Ming Chang
  • Patent number: 10313981
    Abstract: The present invention discloses a gain adjustment method for wireless communication. This method is carried out by a wireless transceiver, and an embodiment of the method comprises the following steps: obtaining at least one transceiving parameter of a wireless connection partner; determining an adaptive power gain according to the at least one transceiving parameter; having an idle power gain of a radio-frequency circuit of the wireless transceiver be the adaptive power gain for a period of time, or having the idle power gain of the radio-frequency circuit be the adaptive power gain until packet transmission operation or packet reception operation takes place within the period of time; and if none of the packet transmission operation and the packet reception operation takes place within the period of time, having the idle power gain of the radio-frequency circuit be an initial power gain right after the period of time.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 4, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wei-Hsuan Chang, Shen-Chung Lee, Chi-Fang Chang, Yu-Nan Lin
  • Patent number: 10101982
    Abstract: Methods for application management in an electronic device are provided. It is first determined whether the application to be installed is listed in a first list, wherein the first list lists a set of applications which are hardware accelerable. The application is then marked as a hardware accelerable application in response to the application being listed in the first list. Thereafter, the application is installed, wherein a hardware acceleration function of the application is enabled to activate a hardware acceleration unit of the electronic device for hardware acceleration during executing the application being marked as the hardware accelerable application.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: October 16, 2018
    Assignee: HTC Corporation
    Inventors: Chung-Chen Peng, Tsung-Wei Lai, Ming-Chao Lee, Chi-Nan Lin, Yi-Chih Chou, Yu-Chi Huang, Jian-Chau Huang, Shang-Che Chen, Han-Kuan Yu, Shih-Ping Lin
  • Publication number: 20150123152
    Abstract: A light-emitting element includes a light-emitting stacked layer including an upper surface, wherein the upper surface includes a first flat region; a protective layer including a current blocking region on the first flat region; and a cap region on the upper surface, wherein the current blocking region is spatially separate from the cap region; and a first electrode covering the current blocking region.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 7, 2015
    Inventors: CHI-NAN LIN, CHIEN-FU SHEN, YU-CHEN YANG, Ching-Tung Tseng, Cheng-Hsiang Ho, Chun-Wei Chang, Chen Ou
  • Publication number: 20140215453
    Abstract: Methods for application management in an electronic device are provided. It is first determined whether the application to be installed is listed in a first list, wherein the first list lists a set of applications which are hardware accelerable. The application is then marked as a hardware accelerable application in response to the application being listed in the first list. Thereafter, the application is installed, wherein a hardware acceleration function of the application is enabled to activate a hardware acceleration unit of the electronic device for hardware acceleration during executing the application being marked as the hardware accelerable application.
    Type: Application
    Filed: November 8, 2013
    Publication date: July 31, 2014
    Applicant: HTC Corporation
    Inventors: Chung-Chen PENG, Tsung-Wei LAI, Ming-Chao LEE, Chi-Nan LIN, Yi-Chih CHOU, Yu-Chi HUANG, Jian-Chau HUANG, Shang-Che CHEN, Han-Kuan YU, Shih-Ping LIN
  • Publication number: 20090197321
    Abstract: The present invention relates to a strain of Escherichia coli (E. coli M2H) for biosynthesis of high yield carotenoids, the steps for obtaining E. coli M2H comprises: purifying the host strain JCL1613 for pCW9/P2IDI; create plasmids for producing carotenoid genes; transform the plasmids into JCL1613; utilizing physical method (UV) to induce and improve JCL1613; select the portions with 99% death rate; utilizing 50 mL shake flask incubation; and go through UV screening to obtain the mutated strain of E. coli M2H.
    Type: Application
    Filed: January 23, 2009
    Publication date: August 6, 2009
    Inventors: Ming-Hsi CHIOU, Mei-Chiao Wu, Ming-Haw Yang, Chi-Nan Lin, Yi-Chen Lu