Patents by Inventor Chi-Nan Yang

Chi-Nan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming power grid structures
    Patent number: 11935833
    Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin
  • Pen
    Patent number: D504153
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: April 19, 2005
    Inventor: Chi-Nan Yang
  • Pen
    Patent number: D482067
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: November 11, 2003
    Inventor: Chi-Nan Yang
  • Pen
    Patent number: D482399
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: November 18, 2003
    Inventor: Chi-Nan Yang