Patents by Inventor Chi On Chui

Chi On Chui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031490
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer on sidewalls of gate spacers disposed over a semiconductor layer, forming a first hafnium-containing gate dielectric layer over the semiconductor layer in a first trench disposed between the gate spacers, removing the sacrificial layer to form a second trench between the gate spacers and the first hafnium-containing gate dielectric layer, forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and on the sidewalls of the gate spacers, annealing the first and the second hafnium-containing gate dielectric layers while simultaneously applying an electric field, and subsequently forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Chi On Chui, Ziwei Fang, Huang-Lin Chao
  • Patent number: 11018256
    Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
  • Patent number: 11011372
    Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yen Peng, Te-Yang Lai, Sai-Hooi Yeong, Chi On Chui
  • Publication number: 20210134971
    Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Ko, Bi-Fen Wu, Chi-On Chui
  • Publication number: 20210134983
    Abstract: A method includes forming a protruding structure, and forming a non-conformal film on the protruding structure using an Atomic Layer Deposition (ALD) process. The non-conformal film includes a top portion directly over the protruding structure, and a sidewall portion on a sidewall of the protruding structure. The top portion has a first thickness, and the sidewall portion has a second thickness smaller than the first thickness.
    Type: Application
    Filed: May 21, 2020
    Publication date: May 6, 2021
    Inventors: Ming-Ho Lin, Cheng-I Lin, Chun-Heng Chen, Chi On Chui
  • Publication number: 20210126101
    Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.
    Type: Application
    Filed: September 11, 2020
    Publication date: April 29, 2021
    Inventors: Kuei-Lun Lin, Yen-Fu Chen, Po-Ting Lin, Chia-Yuan Chang, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20210126099
    Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets.
    Type: Application
    Filed: February 24, 2020
    Publication date: April 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi-On Chui
  • Publication number: 20210126105
    Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.
    Type: Application
    Filed: June 12, 2020
    Publication date: April 29, 2021
    Inventors: Chia-Wei Hsu, Pei Ying Lai, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20210119010
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first source/drain structure and a second source/drain structure in the substrate. The semiconductor device structure includes a gate stack over the substrate and between the first source/drain structure and the second source/drain structure. The gate stack includes a gate dielectric layer and a gate over the gate dielectric layer, a portion of the gate dielectric layer is adjacent to a first sidewall of the gate, the gate stack has a gap between the first sidewall and the portion of the gate dielectric layer, and the gap is a vacuum gap or an air gap.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sai-Hooi YEONG, Chien-Ning YAO, Chi-On CHUI
  • Publication number: 20210115557
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a hydrophobic coating on an inner surface of an exhaust line, connecting the exhaust line to a semiconductor processing chamber, introducing a first precursor into the semiconductor processing chamber, introducing a second precursor into the semiconductor processing chamber, wherein the first precursor reacts with the second precursor to form a layer of oxide material, and pumping the first precursor and the second precursor from the semiconductor processing chamber and through the exhaust line.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Chung-Ting Ko, Amelia Chen, Wan-Chen Hsieh, Ming-Fa Wu, Tai-Chun Huang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 10985266
    Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Yang Lai, Che-Hao Chang, Chi On Chui
  • Patent number: 10978567
    Abstract: The present disclosure describes a method that can eliminate or minimize the formation of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the method includes providing a substrate with fins thereon; depositing an interfacial layer on the fins; depositing a ferroelectric layer on the interfacial layer; depositing a metal gate layer on the ferroelectric layer; exposing the metal gate layer to a metal-halide gas; and performing a post metallization annealing, where the exposing the metal gate layer to the metal-halide gas and the performing the post metallization annealing occur without a vacuum break.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
  • Patent number: 10971627
    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a gate structure, a spacer structure and a source/drain structure that are formed on a surface of the semiconductor layer. The gate structure includes a dielectric structure, a metal structure and an insulator structure. The dielectric structure is formed on the surface of the semiconductor layer. A bottom of the metal structure contacts a top of the dielectric structure. The bottom of the insulator structure contacts a top of the metal structure and the insulator structure protrudes over the top of the metal structure. The spacer structure is configured to extend underneath the bottom of the insulator structure and contact a sidewall of the metal structure. The spacer structure is configured to space between the gate structure and the source/drain structure. The source/drain structure includes a source/drain doped structure, a silicide structure and a metal contact plug.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi Yeong, Chi On Chui, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210098303
    Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
    Type: Application
    Filed: January 3, 2020
    Publication date: April 1, 2021
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20210098458
    Abstract: Provided are a deposition method, a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate and a dielectric structure. The substrate includes at least one fin thereon. The dielectric structure covers the at least one fin. A thickness of the dielectric structure located on a top surface of the at least one fin is greater than a thickness of the dielectric structure located on a sidewall of the at least one fin. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is conformally disposed on the at least one fin. The second dielectric layer is disposed on the first dielectric layer over the top surface of the at least one fin. A thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.
    Type: Application
    Filed: March 2, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-I Lin, Chun-Heng Chen, Ming-Ho Lin, Chi-On Chui
  • Publication number: 20210091077
    Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first gate structure of the first transistor may include a first high-k layer, a first capping layer and a first work function layer sequentially disposed on the substrate, wherein a material of the first work function layer includes Ta. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer, a second capping layer and a second work function layer sequentially disposed on the substrate, wherein the first capping layer and the second capping layer are formed of the same layer, and a material of the second work function layer is different from the material of the first work function layer.
    Type: Application
    Filed: January 30, 2020
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi-On Chui
  • Publication number: 20210091228
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first negative capacitance material over a substrate and patterning the first negative capacitance material to form a fin structure over the substrate. The method also includes forming a source feature and a drain feature in and protruding from a source region and a drain region of the fin structure. The method also includes forming a gate dielectric structure between the source feature and the drain feature to cover a channel region of the fin structure and forming a gate electrode layer over the gate dielectric structure.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng YOUNG, Chih-Yu CHANG, Sai-Hooi YEONG, Chi-On CHUI, Chih-Hao WANG
  • Publication number: 20210091076
    Abstract: A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi-On Chui
  • Publication number: 20210083068
    Abstract: The present disclosure describes a method that can eliminate or minimize the formation of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the method includes providing a substrate with fins thereon; depositing an interfacial layer on the fins; depositing a ferroelectric layer on the interfacial layer; depositing a metal gate layer on the ferroelectric layer; exposing the metal gate layer to a metal-halide gas; and performing a post metallization annealing, where the exposing the metal gate layer to the metal-halide gas and the performing the post metallization annealing occur without a vacuum break.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Chi On CHUI, Huang-Lin CHAO
  • Publication number: 20210083120
    Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Chi On CHUI, Huang-Lin CHAO