Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

Abstract: A semiconductor device includes a fin structure, a metal gate stack, a barrier structure and an epitaxial source/drain region. The fin structure is over a substrate. The metal gate stack is across the fin structure. The barrier structure is on opposite sides of the metal gate stack. The barrier structure comprises one or more passivation layers and one or more barrier layers, and the one or more passivation layers have a material different from a material of the one or more barrier layers. The epitaxial source/drain region is over the barrier structure.

Abstract: A method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ILD) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ILD layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to NH-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to N-terminated, while leaving the surfaces of the bottom portion of the trench being NH-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.

Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.

Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.

Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

Abstract: A semiconductor device includes a substrate, first and second semiconductor strips, a dummy fin structure, first and second channel layers, a gate structure, and crystalline and amorphous hard mask layers. The first and second semiconductor strips extend upwardly from the substrate and each has a length extending along a first direction. The dummy fin structure is laterally between the first and second semiconductor strips. The first and second channel layers extend in the first direction above the first and second semiconductor strips and are arranged in a second direction substantially perpendicular to the substrate. The crystalline hard mask layer extends upwardly from the dummy fin structure and has an U-shaped cross section. The amorphous hard mask layer is in the crystalline hard mask layer. The amorphous hard mask layer has an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor protruding structure over a substrate and surrounding the semiconductor protruding structure with an insulating layer. The method also includes forming a dielectric layer over the insulating layer. The method further includes partially removing the dielectric layer and insulating layer using a planarization process. As a result, topmost surfaces of the semiconductor protruding structure, the insulating layer, and the dielectric layer are substantially level with each other. In addition, the method includes forming a protective layer to cover the topmost surfaces of the dielectric layer. The method includes recessing the insulating layer after the protective layer is formed such that the semiconductor protruding structure and a portion of the dielectric layer protrude from a top surface of a remaining portion of the insulating layer.

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.