Patents by Inventor Chi On Chui

Chi On Chui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220190162
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure also includes a first nanostructure over the fin and a second nanostructure over the first nanostructure. The semiconductor device structure further includes a gate stack wrapping around an upper portion of the fin, the first nanostructure, and the second nanostructure. In addition, the semiconductor device structure includes a first inner spacer between the fin and the first nanostructure and a second inner spacer between the first nanostructure and the second nanostructure. The semiconductor device structure includes a first low dielectric constant structure in the first inner spacer and a second low dielectric constant structure in the second inner spacer. The first low dielectric constant structure is larger than the second low dielectric constant structure.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sai-Hooi YEONG, Chi-On CHUI, Chien-Ning YAO
  • Patent number: 11362002
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Cheng-Lung Hung, Weng Chang, Chi On Chui
  • Publication number: 20220181495
    Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 9, 2022
    Inventors: CHUN-YEN PENG, CHIH-YU CHANG, BO-FENG YOUNG, TE-YANG LAI, SAI-HOOI YEONG, CHI ON CHUI
  • Publication number: 20220173252
    Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 2, 2022
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
  • Publication number: 20220173115
    Abstract: A method of forming a semiconductor device includes: forming a first fin protruding above a substrate; forming first source/drain regions over the first fin; forming a first plurality of nanostructures over the first fin between the first source/drain regions; forming a first gate structure around the first plurality of nanostructures; and forming a first ferroelectric capacitor over and electrically coupled to the first gate structure.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 2, 2022
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11348917
    Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 31, 2022
    Inventors: Chieh-Ping Wang, Tai-Chun Huang, Yung-Cheng Lu, Ting-Gang Chen, Chi On Chui
  • Patent number: 11342334
    Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sai-Hooi Yeong, Chi On Chui, Yu-Ming Lin
  • Patent number: 11335603
    Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh-Ping Wang, Ting-Gang Chen, Bo-Cyuan Lu, Tai-Chun Huang, Chi On Chui
  • Patent number: 11335806
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure over the substrate, and a FeFET device over a first region of the substrate. The FeFET includes a first gate stack across the first fin structure. The semiconductor device structure also includes first gate spacer layers alongside the first gate stack, and a ferroelectric layer over the first gate stack. At least a portion of the ferroelectric layer is located between upper portions of the first gate spacer layers and is adjacent to the first gate stack.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sai-Hooi Yeong, Chi-On Chui, Chien-Ning Yao
  • Publication number: 20220149169
    Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is vertically disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. An area of the gate stack projected on a top surface of the substrate is within an area of the bottom dielectric layer projected on the top surface of the substrate.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi-On Chui
  • Publication number: 20220149182
    Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Inventors: Te-Yang Lai, Chun-Yen Peng, Sai-Hooi Yeong, Chi On Chui
  • Publication number: 20220140101
    Abstract: A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Inventors: Hsin-Yi Lee, Weng Chang, Chi On Chui
  • Publication number: 20220140151
    Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 5, 2022
    Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chien Ning Yao, Chi On Chui
  • Patent number: 11322505
    Abstract: A method of forming a semiconductor device includes: forming a first fin protruding above a substrate; forming first source/drain regions over the first fin; forming a first plurality of nanostructures over the first fin between the first source/drain regions; forming a first gate structure around the first plurality of nanostructures; and forming a first ferroelectric capacitor over and electrically coupled to the first gate structure.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11316047
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Ko, Bo-Cyuan Lu, Jr-Hung Li, Chi-On Chui
  • Patent number: 11316034
    Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20220123003
    Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui, Chun-Chieh Lu, Yu-Ming Lin
  • Publication number: 20220123124
    Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.
    Type: Application
    Filed: February 2, 2021
    Publication date: April 21, 2022
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
  • Publication number: 20220122887
    Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui, Yu-Ming Lin
  • Patent number: 11309398
    Abstract: The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, a multilayer gate dielectric stack over the fin, wherein the multilayer gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, and a gate over the multilayer gate dielectric stack.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Yen Peng, Te-Yang Lai, Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui