Abstract: A method includes forming a plurality of semiconductor nanostructures comprising a lower semiconductor nanostructure and a topmost semiconductor nanostructure over the lower semiconductor nanostructure, forming interfacial layers contacting the plurality of semiconductor nanostructures, and depositing high-k dielectric layers encircling the interfacial layers. A topmost high-k dielectric layer of the high-k dielectric layers encircling the topmost semiconductor nanostructure includes a topmost horizontal portion overlapping the topmost semiconductor nanostructure, a bottom horizontal portion overlapped by the topmost semiconductor nanostructure, and a sidewall portion on a sidewall of the topmost semiconductor nanostructure. A first one of the topmost horizontal portion, the bottom horizontal portion, and the sidewall portion has a first thickness. A second one of the topmost horizontal portion, the bottom horizontal portion, and the sidewall portion has a second thickness smaller than the first thickness.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a hydrophobic coating on an inner surface of an exhaust line, connecting the exhaust line to a semiconductor processing chamber, introducing a first precursor into the semiconductor processing chamber, introducing a second precursor into the semiconductor processing chamber, wherein the first precursor reacts with the second precursor to form a layer of oxide material, and pumping the first precursor and the second precursor from the semiconductor processing chamber and through the exhaust line.

Abstract: Semiconductor structures and methods are provided. An example method includes receiving a workpiece that includes a substrate, first channel members over a first region of the substrate, second channel members over a second region of the substrate, and third channel members over a third region of the substrate, depositing a first gate dielectric layer to wrap around each of the first channel members, each of the second channel members, and each of the third channel members, selectively depositing a first dipole layer to wrap around each of the third channel members, performing a first anneal process to drive a first dopant in the first dipole layer into the first gate dielectric layer around the third channel members, removing the first dipole layer, and after the removing, depositing a second gate dielectric layer to wrap around the first channel members, the second channel members, and the third channel members.

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing an aluminum nitride layer on the gate dielectric, depositing an aluminum oxide layer on the aluminum nitride layer, performing an annealing process to drive aluminum in the aluminum nitride layer into the gate dielectric, removing the aluminum oxide layer and the aluminum nitride layer, and forming a gate electrode on the gate dielectric.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a transistor over the first wafer; bonding a first wafer to a second wafer; trimming an edge region of the first wafer along a circular trimming path, wherein a center of the circular trimming path is offset from a center of the second wafer in a top view; after trimming the edge region of the first wafer, thinning down the first wafer; and after thinning down the first wafer, forming a backside conductive feature electrically connected to the transistor.

Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked, removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers, selectively forming a passivation layer on sidewalls of the first semiconductor layers, forming a dielectric spacer on sidewalls of the second semiconductor layers and filling in the cavities, wherein the passivation layer is exposed. The method also includes removing the passivation layer, and forming an epitaxial source/drain feature so that the epitaxial source/drain feature is in contact with the first semiconductor layers and the dielectric spacers.

Abstract: A method includes forming a plurality of semiconductor nanostructures, and forming a hard mask comprising a top portion over the plurality of semiconductor nanostructures, inner portions between the plurality of semiconductor nanostructures, and sidewall portions on sidewalls of the plurality of semiconductor nanostructures. The method further includes etching the sidewall portions of the hard mask, with at least a top portion of the hard mask remaining, performing a first oxidation process to oxidize sidewall portions of the semiconductor nanostructures to form first oxide layers, removing the top portion and the inner portions of the hard mask, and performing a second oxidation process to oxidize top portions and the bottom portions of the semiconductor nanostructures to form second oxide layers. The second oxide layers comprise the first oxide layers. The second oxide layers encircle remaining portions of the plurality of semiconductor nanostructures.

Abstract: A semiconductor device includes a fin structure, a metal gate stack, a barrier structure and an epitaxial source/drain region. The fin structure is over a substrate. The metal gate stack is across the fin structure. The barrier structure is on opposite sides of the metal gate stack. The barrier structure comprises one or more passivation layers and one or more barrier layers, and the one or more passivation layers have a material different from a material of the one or more barrier layers. The epitaxial source/drain region is over the barrier structure.

Abstract: In method of manufacturing a semiconductor device, an opening is formed over a first conductive layer in a dielectric layer, a second conductive layer is formed over the first conductive layer in the opening without forming the second conductive layer on at least an upper surface of the dielectric layer, a third conductive layer is formed over the second conductive layer in the opening without forming the third conductive layer on at least an upper surface of the dielectric layer, and an upper layer is formed over the third conductive layer in the opening.

Abstract: Flowable low-k and ultra low-k dielectric materials may be used as materials for inner spacers to prevent formation of inner spacer defects. A flowable deposition process (e.g., a flowable chemical vapor deposition (FCVD) process) may be used to deposit the flowable low-k and ultra low-k dielectric materials to avoid inner spacer defect formation. Ratios of precursors to reactants used in the flowable deposition process may be tuned to increase flowability to prevent generation of seams and/or voids in the inner spacers. If defect formation is avoided, processes to trim and/or clean nanostructure channel surfaces prior to epitaxial growth of source/drain regions may be performed for a requisite amount of time without concern that defects will be enlarged. Due to the lack of defects in inner spacers formed using the techniques described herein, the inner spacers may provide increased protection from parasitic capacitance between gates and source/drain regions in nanostructure transistors.

Abstract: A fin structure is formed over a substrate. An insulation feature is formed over the substrate and laterally with respect to the fin structure. A dielectric layer of SiON is formed over the insulation feature and over the fin structure. A dummy gate structure is formed over the insulation feature, and the dielectric layer separates the dummy gate structure from the insulation feature.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

Abstract: A method includes forming a capacitor, which includes forming a first capacitor electrode, forming a first capacitor insulator over the first capacitor electrode, and forming a second capacitor electrode over and contacting the first capacitor insulator. The formation of the first capacitor insulator includes oxidizing a top surface layer of the first capacitor electrode to form a metal oxide layer on the first capacitor electrode, depositing an aluminum oxide layer through a first ALD process having a first plurality of ALD cycles, with the first plurality of ALD cycles having a first ALD cycle number, and depositing a high-k dielectric layer over the aluminum oxide layer. The high-k dielectric layer is deposited through a second ALD process having a second ALD cycle number different from the first ALD cycle number.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other; forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species; implanting fluorine ions into the source/drain epitaxial structure; after implanting fluorine ions into the source/drain epitaxial structure, performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and forming a source/drain contact over the source/drain epitaxial structure.

Abstract: A method includes forming a first electrode, performing a first treatment process on a first oxide layer over the first electrode, wherein the first treatment process is performed using a first process gas comprising ammonia, depositing a high-k dielectric layer over the first oxide layer, forming a second electrode over the high-k dielectric layer, forming a first contact plug electrically connecting to the first electrode, and forming a second contact plug electrically connecting to the second electrode.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a first work-function layer over the gate dielectric layer. The first work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.

Abstract: A method of forming a semiconductor device includes forming a first layer over a semiconductor fin and forming a second layer over the first layer. The first layer is a first material and the second layer is a second material different from the first layer. The second layer is thicker on a top of the semiconductor fin than along a sidewall of the semiconductor fin. The method further includes performing an oxidation process, the oxidation process oxidizing at least a portion of the second layer, and patterning the second layer and the first layer.

Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.