Patents by Inventor CHI PAN

CHI PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113588
    Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Pan, Kuo-Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Yu-Te Su, Kuan-Wei Lin
  • Patent number: 12253776
    Abstract: A method of forming an electronic device including: providing an assembly, wherein the assembly includes a substrate, an optical film, a plurality of color filters and a defect, wherein the plurality of color filters and the defect are disposed between the substrate and the optical film; and using a laser pulse to form a first processed area that corresponds to the defect in the optical film, wherein the first processed area at least partially overlaps at least two of the plurality of color filters.
    Type: Grant
    Filed: March 25, 2024
    Date of Patent: March 18, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
  • Publication number: 20250052515
    Abstract: The temperature control apparatus comprises a heat exchanging unit and a working fluid. The heat exchanging unit is independently disposed and divided into a first heat exchanging portion disposed at a first environment and a second heat exchanging portion disposed at a second environment. The heat exchanging unit has a plurality of heat-dissipating fins and a pipe running in the first heat exchanging portion and then running in the second heat exchanging portion. The pipe has an inlet and an outlet disposed in the first and second heat exchanging portions respectively. The pipe has a larger pipe diameter around the inlet and the outlet, and has a smaller pipe diameter away from the inlet and the outlet. The smaller pipe diameter of the pipe has the capillary function for regulating the pressure of the working fluid in the first and second heat exchanging portions.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Hsueh-Chi PAN, Tse-Hsin WANG, Chia-Wei CHEN, Ying-Chi CHEN
  • Patent number: 12183637
    Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chi Pan, Kuo-Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Yu-Te Su, Kuan-Wei Lin
  • Publication number: 20240352584
    Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 24, 2024
    Inventors: Yu-Hsuan WU, Teng Mao WANG, Yan-Chi PAN, Yi-Jiun SHIU, Jrjyan Jerry CHEN, Cheng-yuan LIN, Hsiao-Ling YANG, Yu-Min WANG, Wen-Hao WU
  • Publication number: 20240309340
    Abstract: An engineered DNA polymerase, with increased property for single molecule sequencing compared to a wild-type DNA polymerase, comprising a combination of mutation sites and functional domains, wherein the combination of mutation sites and functional domains includes thermostable mutation sites, low Kd mutation sites, exonuclease-deficient sites and DNA binding domains.
    Type: Application
    Filed: January 10, 2024
    Publication date: September 19, 2024
    Applicant: Personal Genomics Taiwan, Inc.
    Inventors: Dalton Chen, Ya-Chen Chen, Yu-Husan Lin, Yi-Ting Chou, Ting-Yueh Tsai, Chi-Fu Yen, Chao-Chi Pan
  • Publication number: 20240264501
    Abstract: A method of forming an electronic device including: providing an assembly, wherein the assembly includes a substrate, an optical film, a plurality of color filters and a defect, wherein the plurality of color filters and the defect are disposed between the substrate and the optical film; and using a laser pulse to form a first processed area that corresponds to the defect in the optical film, wherein the first processed area at least partially overlaps at least two of the plurality of color filters.
    Type: Application
    Filed: March 25, 2024
    Publication date: August 8, 2024
    Inventors: Tai-Chi PAN, Chin-Lung TING, I-Chang LIANG, Chih-Chiang CHANG CHIEN, Po-Wen LIN, Kuang-Ming FAN, Sheng-Nan CHEN
  • Publication number: 20240186390
    Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a gate dielectric layer disposed over the fin structure. The semiconductor device includes an interfacial layer over a top portion of the gate dielectric layer. A bottom portion of gate dielectric layer is free of contact with the interfacial layer. The semiconductor device includes a gate structure straddling the fin structure.
    Type: Application
    Filed: February 12, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi PAN, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11966133
    Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: April 23, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
  • Patent number: 11923428
    Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Pan, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20230420538
    Abstract: A semiconductor device includes a plurality of fin structures disposed over a substrate and a work function alloy layer disposed over each fin structure of the plurality of fin structures. The plurality of fin structures includes a first fin structure and a second fin structure. A content of a first element in a first portion of the work function alloy layer, which portion is disposed over the first fin structure, is different from a content of the first element in a second portion of the work function alloy layer, which portion is disposed over the second fin structure.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi PAN, Kuan-Wei Lin, Chun-Neng Lin, Yu-Shih Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20230378360
    Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Yu-Chi Pan, Chun-Ming Yang, Chun-Sheng Liang, Ying-Liang Chuang, Ming-Hsi Yeh
  • Publication number: 20230371696
    Abstract: A seat apparatus having a simulated force feedback and a method for simulating a force sensation of driving are provided. The seat apparatus includes a seating unit, a rotary platform, and a realistic seat pallet. The seating unit includes a seat pan. The rotary platform includes a chassis and a rotary motive module. The seat pan is disposed on the chassis along a rotation axis in an inclinable manner. The rotary motive module can control the seat pan to have a forward or rearward inclined angle. The realistic seat pallet is disposed on the seat pan, and includes a movable contact cushion and a pallet motive module. Through the pallet motive module, the movable contact cushion is slidable relative to the seat pan. The pallet motive module can control the movable contact cushion to have left and right displacements, front and rear displacements, angular displacements, or yaw rotations.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 23, 2023
    Inventors: SHIANG-FONG CHEN, Bo-Ting Lin, CHI PAN, TZU-YUAN YU
  • Patent number: 11810978
    Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Yu-Chi Pan, Chun-Ming Yang, Chun-Sheng Liang, Ying-Liang Chuang, Ming-Hsi Yeh
  • Publication number: 20230335443
    Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Pan, Kuo-Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Yu-Te Su, Kuan-Wei Lin
  • Publication number: 20230288764
    Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Inventors: Tai-Chi PAN, Chin-Lung TING, I-Chang LIANG, Chih-Chiang CHANG CHIEN, Po-Wen LIN, Kuang-Ming FAN, Sheng-Nan CHEN
  • Patent number: 11733378
    Abstract: The present disclosure provides a detection system and a detection method. The microphone of the detection system receives the response signal formed according to the shape of the sealed cavity. The conversion unit transfers the response signal in the time domain to the frequency domain signal in the frequency domain. The calculation unit obtains every frequency value corresponding to the frequency gradient being zero of each frequency waveform which is chosen of the response signal. The average unit averages every frequency value corresponding to the frequency gradient being zero of each chosen frequency waveform into the average frequency value and outputs an average frequency value. The determination unit determines whether the average frequency value is located in the corresponding frequency tolerance range, so that the wearing status of the in-ear earphone is confirmed.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: August 22, 2023
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chung-Han Lin, Yueh-Hsiang Chen, Kun-Chi Pan
  • Publication number: 20230253469
    Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 10, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: YU-CHI PAN, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11715670
    Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Chi Pan, Kuo-Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Yu-Te Su, Kuan-Wei Lin
  • Patent number: D1002229
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 24, 2023
    Assignee: Sheng Tai Brassware Co., Ltd.
    Inventors: Chin-Chi Pan, Chi Yuan Lee