Patents by Inventor CHI-RAY HUANG

CHI-RAY HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240241567
    Abstract: A micro-controller circuit including a central processing unit (CPU), a plurality of function circuits, a management circuit, and a driving circuit is provided. The CPU is in a first power domain. The function circuits are in a second power domain. In response to the first power domain being powered-off, the function circuits operate normally to generate an event trigger signal. The management circuit reads a look-up table to provide at least one management signal in response to the first power domain being powered-off and the event trigger signal is enabled. The driving circuit adjusts at least one driving signal according to the management signal and provides the driving signal to at least one of the function circuits.
    Type: Application
    Filed: January 9, 2024
    Publication date: July 18, 2024
    Inventor: Chi-Ray HUANG
  • Patent number: 11984893
    Abstract: A data retention circuit is provided in the invention. The data retention circuit includes a master latch circuit, a slave latch circuit, and a control circuit. The control circuit is coupled to the master latch circuit and the slave latch circuit and receives a clock signal from a clock circuit and a power management signal from a power management unit (PMU). In a normal operation mode, the control circuit transmits the clock signal to the master latch circuit and the slave latch circuit. In sleep mode, power to the master latch circuit is switched off and the control circuit transmits the power management signal to the slave latch circuit.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: May 14, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Chi-Ray Huang
  • Publication number: 20240019924
    Abstract: A control device includes a first area, a second area and a third area. The first area includes a peripheral unit, a storage unit and a control unit. The second area includes a peripheral unit, an access unit, a storage unit and a control unit. The third area includes an operating unit, a peripheral unit, an access unit, a storage unit and a control unit. In an ultra-low-power mode, a low-power mode and a high-speed mode, a first working voltage and a first clock signal are provided to the first area. In the low-power mode or the high-speed mode, the first working voltage and a second clock signal are provided to the second area. In the high-speed mode, the first working voltage and a third clock signal are provided to the third area.
    Type: Application
    Filed: May 22, 2023
    Publication date: January 18, 2024
    Inventor: Chi-Ray HUANG
  • Patent number: 11784635
    Abstract: A control circuit including a timer circuit and a voltage monitor circuit is provided. The timer circuit enables a trigger signal every a fixed time interval in response to a wake-up event. The voltage monitor circuit is configured to determine whether the operation voltage reaches the expected voltage and includes a signal-generating circuit, a first delay circuit, a second delay circuit, and a determination circuit. The signal-generating circuit generates a reference signal according to the trigger signal. The first delay circuit receives the operation voltage and delays the reference signal to generate a first delay signal. The second delay circuit delays the trigger signal to generate a second delay signal. The determination circuit enables a wake-up signal according to the reference signal, the first delay signal, and the second delay signal in response to the wake-up event.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: October 10, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Hen-Kai Chang, Chi-Ray Huang
  • Publication number: 20230208406
    Abstract: A data retention circuit is provided in the invention. The data retention circuit includes a master latch circuit, a slave latch circuit, and a control circuit. The control circuit is coupled to the master latch circuit and the slave latch circuit and receives a clock signal from a clock circuit and a power management signal from a power management unit (PMU). In a normal operation mode, the control circuit transmits the clock signal to the master latch circuit and the slave latch circuit. In sleep mode, power to the master latch circuit is switched off and the control circuit transmits the power management signal to the slave latch circuit.
    Type: Application
    Filed: November 25, 2022
    Publication date: June 29, 2023
    Inventor: Chi-Ray HUANG
  • Publication number: 20230206961
    Abstract: An electronic device includes at least two logic circuits, at least two memories, and at least two power switches. The logic circuits are stacked on each other and electrically connected to each other, and they are electrically connected between a power source and a ground. The memories are stacked on each other and electrically coupled to each other, and they are electrically connected between the power source and the ground. The power switches are connected in series between the respective logic circuits and the respective memories. The power switches cut off or maintain the electrical connection between the logic circuits and between the memories, according to a control signal.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 29, 2023
    Inventor: Chi-Ray HUANG
  • Patent number: 10763860
    Abstract: A data retention circuit includes a power switch, a first inverter and a second inverter. The power switch has a first connection terminal coupled to a power voltage, and a second connection terminal coupled to the first power terminal and a second power terminal of a second inverter. The second input terminal and the second output terminal of the second inverter are coupled to the first output terminal and the first input terminal of the first inverter, respectively. In a sleep mode, the power switch and the transistor are turned off, a first leakage current flows between the first connection terminal and the second connection terminal, a second leakage current flows between the first power terminal and the first output terminal, and the first and the second leakage currents form a steady-state voltage, higher than or equal to a data retention voltage, on a second connection terminal.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: September 1, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Chi-Ray Huang
  • Publication number: 20200212912
    Abstract: A data retention circuit includes a power switch, a first inverter and a second inverter. The power switch has a first connection terminal coupled to a power voltage, and a second connection terminal coupled to the first power terminal and a second power terminal of a second inverter. The second input terminal and the second output terminal of the second inverter are coupled to the first output terminal and the first input terminal of the first inverter, respectively. In a sleep mode, the power switch and the transistor are turned off, a first leakage current flows between the first connection terminal and the second connection terminal, a second leakage current flows between the first power terminal and the first output terminal, and the first and the second leakage currents form a steady-state voltage, higher than or equal to a data retention voltage, on a second connection terminal.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 2, 2020
    Inventor: Chi-Ray HUANG
  • Publication number: 20170213588
    Abstract: A memory comprised of a plurality of single port SRAM memory cells, each driven by two word lines in an asynchronous manner has a hold mode, a read mode and a write mode. Each of the single port SRAM memory cells includes a first write switch, a second write switch and a latch. The first write switch is electrically connected to a first word line and is turned on by a first turn-on signal transmitted by the first word line. The second write switch is electrically connected to a second word line and is turned on by a second turn-on signal transmitted by the second word line. When the memory is in the write mode, the second write switch is turned on by the second turn-on signal having a delay with respect to the first turn-on signal, thereby blocking the pseudo read of the unselected memory cell.
    Type: Application
    Filed: September 14, 2016
    Publication date: July 27, 2017
    Inventors: LIH-YIH CHIOU, CHI-RAY HUANG
  • Patent number: 9715922
    Abstract: A memory comprised of a plurality of single port SRAM memory cells, each driven by two word lines in an asynchronous manner has a hold mode, a read mode and a write mode. Each of the single port SRAM memory cells includes a first write switch, a second write switch and a latch. The first write switch is electrically connected to a first word line and is turned on by a first turn-on signal transmitted by the first word line. The second write switch is electrically connected to a second word line and is turned on by a second turn-on signal transmitted by the second word line. When the memory is in the write mode, the second write switch is turned on by the second turn-on signal having a delay with respect to the first turn-on signal, thereby blocking the pseudo read of the unselected memory cell.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: July 25, 2017
    Assignee: National Cheng Kung University
    Inventors: Lih-Yih Chiou, Chi-Ray Huang
  • Patent number: 9123436
    Abstract: An adaptive data-retention-voltage regulating system for static random-access memory (SRAMs) is revealed. The system includes a power supply unit, a data-retention-voltage (DRV) monitor cell for monitoring static noise margin (SNM) of SRAM, a data loss detector for generating a data loss signal, and a dynamic regulating controller that receives the data loss signal for generating a refresh signal and a switch signal. The DVR monitor cell consists of a DRV monitor circuit mounted with a plurality of memory cells, a reset signal generating circuit for resetting the DRV monitor circuit, and an adaptive variation control circuit that generates noise bias according to leakage current to adjust reaction speed of the DRV monitor circuit correspondingly.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 1, 2015
    Assignee: National Cheng Kung University
    Inventors: Lih-Yih Chiou, Chi-Ray Huang, Kuan-Lin Wu
  • Patent number: 9094002
    Abstract: An in situ pulse-based delay variation monitor that predicts timing errors caused by process and environmental variations is revealed. The monitor includes a sequential storage device having a mater storage device and a slave storage device, a transition detector that is electrically connected to a node set on an electrical connection pathway from a master storage device to the slave storage device, and a warning signal generator electrically connected to the transition detector. The transition detector receives output of the master storage device to form a warning area by delay buffer, and generates a pulse width output correspondingly according to transition of the data input. Thus the warning signal generator generates a warning signal according to logic action at the pulse width and the clock input when the data input reaches the warning area. Thereby timing errors caused by static process variations and dynamic environmental variations are predicted.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: July 28, 2015
    Assignee: National Cheng Kung University
    Inventors: Lih-Yih Chiou, Chi-Ray Huang, Ming-Hung Wu
  • Publication number: 20150092477
    Abstract: An adaptive data-retention-voltage regulating system for static random-access memory (SRAMs) is revealed. The system includes a power supply unit, a data-retention-voltage (DRV) monitor cell for monitoring static noise margin (SNM) of SRAM, a data loss detector for generating a data loss signal, and a dynamic regulating controller that receives the data loss signal for generating a refresh signal and a switch signal. The DVR monitor cell consists of a DRV monitor circuit mounted with a plurality of memory cells, a reset signal generating circuit for resetting the DRV monitor circuit, and an adaptive variation control circuit that generates noise bias according to leakage current to adjust reaction speed of the DRV monitor circuit correspondingly.
    Type: Application
    Filed: July 18, 2014
    Publication date: April 2, 2015
    Inventors: LIH-YIH CHIOU, CHI-RAY HUANG, KUAN-LIN WU
  • Publication number: 20140152344
    Abstract: An in situ pulse-based delay variation monitor that predicts timing errors caused by process and environmental variations is revealed. The monitor includes a sequential storage device having a mater storage device and a slave storage device, a transition detector that is electrically connected to a node set on an electrical connection pathway from a master storage device to the slave storage device, and a warning signal generator electrically connected to the transition detector. The transition detector receives output of the master storage device to form a warning area by delay buffer, and generates a pulse width output correspondingly according to transition of the data input. Thus the warning signal generator generates a warning signal according to logic action at the pulse width and the clock input when the data input reaches the warning area. Thereby timing errors caused by static process variations and dynamic environmental variations are predicted.
    Type: Application
    Filed: November 1, 2013
    Publication date: June 5, 2014
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: LIH-YIH CHIOU, CHI-RAY HUANG, MING-HUNG WU