Patents by Inventor Chi-Ruei YEH
Chi-Ruei YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230260792Abstract: The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.Type: ApplicationFiled: April 20, 2023Publication date: August 17, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin Hsiang TSENG, Chi-Ruei YEH, Tsung-Yu CHIANG
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Publication number: 20230245921Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; forming a fin structure on the substrate; forming a first dummy gate on the fin structure; forming a trench to penetrate the first dummy gate and the fin structure; forming a dielectric stack in the trench; removing a top portion of the dielectric stack in the trench to leave a lower portion of the dielectric stack in the trench; and forming a protective layer in the trench and directly on the lower portion of the dielectric stack.Type: ApplicationFiled: January 28, 2022Publication date: August 3, 2023Inventors: KUI-YU CHEN, CHI-RUEI YEH, TSUNG-YU CHIANG
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Publication number: 20230238381Abstract: A method includes forming an n-type Fin-Field Effect Transistor (FinFET) and a p-type FinFET. The forming of the n-type FinFFT includes: forming a first auxiliary gate stack over a first semiconductor fin; forming an n-type source/drain region on the first semiconductor fin adjacent to the first auxiliary gate stack; and performing a first etch to form a first recess with a first depth on a first top surface of the n-type source/drain region. The forming of the p-type FinFFT includes: forming a second auxiliary gate stack over a second semiconductor fin; forming a p-type source/drain region on the second semiconductor fin adjacent to the second auxiliary gate stack; and performing a second etch to form a second recess with a second depth on a second top surface of the p-type source/drain region. The first depth is greater than the second depth.Type: ApplicationFiled: January 27, 2022Publication date: July 27, 2023Inventors: LI-WEI LIU, CHI-RUEI YEH, TSUNG-YU CHIANG
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Patent number: 11637018Abstract: The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.Type: GrantFiled: October 27, 2020Date of Patent: April 25, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsinhsiang Tseng, Chi-Ruei Yeh, Tsung-Yu Chiang
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Publication number: 20220344265Abstract: A semiconductor device includes a gate structure disposed in a first dielectric layer, a conductive segment disposed in the first dielectric layer and separated from the gate structure, a second dielectric layer disposed over the first dielectric layer, a first contact penetrating the second dielectric layer and electrically connected to the gate structure, a second contact penetrating the second dielectric layer and electrically connected to the conductive segment, and a silicon nitride-based layer surrounding at least one of the first and second contacts and connected between the second dielectric layer and the at least one of the first and second contacts. A method for making the semiconductor device is also provided.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsinhsiang TSENG, Chi-Ruei YEH, Tsung-Yu CHIANG
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Publication number: 20220130678Abstract: The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.Type: ApplicationFiled: October 27, 2020Publication date: April 28, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsinhsiang Tseng, Chi-Ruei Yeh, Tsung-Yu Chiang
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Patent number: 10867852Abstract: Provided is a semiconductor device including a substrate, a gate structure, a dielectric layer, an etch stop layer, and an adhesion layer. The gate structure is formed over the substrate. The dielectric layer is formed aside the gate structure. The adhesion layer overlays a top surface of the gate structure and extends to a first top surface of the dielectric layer. The etch stop layer is over the adhesion layer and in contact with a second top surface of the dielectric layer.Type: GrantFiled: December 15, 2015Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ruei Yeh, Wen-Hsin Chan, Kang-Min Kuo
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Patent number: 10868133Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.Type: GrantFiled: October 28, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Ruei Yeh, Chih-Lin Wang, Kang-Min Kuo
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Publication number: 20200058756Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.Type: ApplicationFiled: October 28, 2019Publication date: February 20, 2020Inventors: Chi-Ruei YEH, Chih-Lin WANG, Kang-Min KUO
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Patent number: 10461169Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.Type: GrantFiled: March 5, 2018Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Ruei Yeh, Chih-Lin Wang, Kang-Min Kuo
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Publication number: 20180197969Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Inventors: Chi-Ruei YEH, Chih-Lin WANG, Kang-Min KUO
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Patent number: 9911821Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a metal gate electrode structure over the semiconductor substrate. The semiconductor device structure includes an insulating layer over the semiconductor substrate and surrounding the metal gate electrode structure. The semiconductor device structure includes a first metal nitride layer over a first top surface of the metal gate electrode structure and in direct contact with the metal gate electrode structure. The first metal nitride layer includes a nitride material of the metal gate electrode structure.Type: GrantFiled: November 13, 2015Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Ruei Yeh, Chih-Lin Wang, Kang-Min Kuo
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Publication number: 20170170067Abstract: Provided is a semiconductor device including a substrate, a gate structure, a dielectric layer, an etch stop layer, and an adhesion layer. The gate structure is formed over the substrate. The dielectric layer is formed aside the gate structure. The adhesion layer overlays a top surface of the gate structure and extends to a first top surface of the dielectric layer. The etch stop layer is over the adhesion layer and in contact with a second top surface of the dielectric layer.Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Inventors: Chi-Ruei Yeh, Wen-Hsin Chan, Kang-Min Kuo
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Publication number: 20170141205Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a metal gate electrode structure over the semiconductor substrate. The semiconductor device structure includes an insulating layer over the semiconductor substrate and surrounding the metal gate electrode structure. The semiconductor device structure includes a first metal nitride layer over a first top surface of the metal gate electrode structure and in direct contact with the metal gate electrode structure. The first metal nitride layer includes a nitride material of the metal gate electrode structure.Type: ApplicationFiled: November 13, 2015Publication date: May 18, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Ruei YEH, Chih-Lin WANG, Kang-Min KUO