Patents by Inventor Chi Seong Kim
Chi Seong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903129Abstract: A printed circuit board includes: a first insulating material; and a second insulating material disposed on one surface of the first insulating material, and including first and second cavities having depths different from each other. At least one groove portion is disposed in a side surface of each of the first and second cavities.Type: GrantFiled: March 10, 2022Date of Patent: February 13, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Chi Seong Kim, Won Seok Lee, Guh Hwan Lim, Jin Uk Lee, Jin Oh Park
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Publication number: 20230199976Abstract: A printed circuit board includes a first insulating layer having a through cavity and containing an insulating material. A length between one side surface and the other side surface opposite to the one side surface of the through cavity is greater than a thickness of the first insulating layer, and the first insulating layer includes a recess located in each of an upper edge and a lower edge of the one side surface of the through cavity.Type: ApplicationFiled: April 22, 2022Publication date: June 22, 2023Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Guh Hwan LIM, Chi Seong KIM, Won Seok LEE, Jin Oh PARK, Yu Mi KIM, Sang Yun LEE, Eun Sun KIM
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Publication number: 20230141270Abstract: A printed circuit board includes: a first insulating material; and a second insulating material disposed on one surface of the first insulating material, and including first and second cavities having depths different from each other. At least one groove portion is disposed in a side surface of each of the first and second cavities.Type: ApplicationFiled: March 10, 2022Publication date: May 11, 2023Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Chi Seong Kim, Won Seok Lee, Guh Hwan Lim, Jin Uk Lee, Jin Oh Park
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Patent number: 11641715Abstract: A printed circuit board includes a first insulating layer; a protective filler layer disposed on one surface of the first insulating layer; a first wiring layer disposed on the one surface of the first insulating layer and having a pad protruding with respect to the protective filler layer; a first via passing through the first insulating layer and contacting the pad; and a second insulating layer disposed on the first wiring layer and the protective filler layer, and having a cavity exposing the pad and at least a portion of the protective filler layer, respectively.Type: GrantFiled: September 16, 2021Date of Patent: May 2, 2023Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Eun Sun Kim, Jin Uk Lee, Young Hun You, Chi Seong Kim
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Patent number: 11490503Abstract: A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.Type: GrantFiled: March 17, 2021Date of Patent: November 1, 2022Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Chang Hwa Park, Chi Seong Kim, Eun Heay Lee, Yo Han Song, Gun Hwi Hyung, Jae Heun Lee, Deok Man Kang, Jin Oh Park
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Publication number: 20220322533Abstract: A printed circuit board includes a first insulating layer; a protective filler layer disposed on one surface of the first insulating layer; a first wiring layer disposed on the one surface of the first insulating layer and having a pad protruding with respect to the protective filler layer; a first via passing through the first insulating layer and contacting the pad; and a second insulating layer disposed on the first wiring layer and the protective filler layer, and having a cavity exposing the pad and at least a portion of the protective filler layer, respectively.Type: ApplicationFiled: September 16, 2021Publication date: October 6, 2022Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Eun Sun Kim, Jin Uk Lee, Young Hun You, Chi Seong Kim
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Publication number: 20220022310Abstract: A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.Type: ApplicationFiled: March 17, 2021Publication date: January 20, 2022Inventors: Chang Hwa Park, Chi Seong Kim, Eun Heay Lee, Yo Han Song, Gun Hwi Hyung, Jae Heun LEE, Deok Man Kang, Jin Oh Park
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Patent number: 10902994Abstract: A coil electronic component includes a body including a plurality of insulating layers and coil patterns disposed on the insulating layers, and external electrodes formed on external surfaces of the body and connected to the coil patterns, wherein the external electrodes include first layers being electroless plating layers and second layers formed on the first layers and having a form in which metal particles are dispersed in a polymer base, respectively.Type: GrantFiled: May 24, 2018Date of Patent: January 26, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Chi Seong Kim, Jun Il Kang, Sa Yong Lee, Gun Hwi Hyung
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Publication number: 20190115145Abstract: A coil electronic component includes a body including a plurality of insulating layers and coil patterns disposed on the insulating layers, and external electrodes formed on external surfaces of the body and connected to the coil patterns, wherein the external electrodes include first layers being electroless plating layers and second layers formed on the first layers and having a form in which metal particles are dispersed in a polymer base, respectively.Type: ApplicationFiled: May 24, 2018Publication date: April 18, 2019Inventors: Chi Seong KIM, Jun Il KANG, Sa Yong LEE, Gun Hwi HYUNG
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Patent number: 9743508Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.Type: GrantFiled: September 8, 2015Date of Patent: August 22, 2017Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dong Jun Lee, Dong Ju Jeon, Jung Youn Pang, Seong Min Cho, Chi Seong Kim
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Publication number: 20150382452Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.Type: ApplicationFiled: September 8, 2015Publication date: December 31, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dong Jun LEE, Dong Ju JEON, Jung Youn PANG, Seong Min CHO, Chi Seong KIM
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Patent number: 9150002Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.Type: GrantFiled: June 25, 2012Date of Patent: October 6, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dong Jun Lee, Dong Ju Jeon, Jung Youn Pang, Seong Min Cho, Chi Seong Kim
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Patent number: 8946911Abstract: There is provided an electrode pad including: a connection terminal part; a first plating layer including palladium phosphorus (Pd—P) formed on the connection terminal part; and a second plating layer including palladium (Pd) formed on the first plating layer.Type: GrantFiled: December 6, 2012Date of Patent: February 3, 2015Assignee: Samsung Electro-Machanics Co., Ltd.Inventors: Jung Youn Pang, Shimoji Teruaki, Eun Heay Lee, Seong Min Cho, Chi Seong Kim
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Publication number: 20140087205Abstract: There is provided an electrode pad including: a connection terminal part; a first plating layer including palladium phosphorus (Pd—P) formed on the connection terminal part; and a second plating layer including palladium (Pd) formed on the first plating layer.Type: ApplicationFiled: December 6, 2012Publication date: March 27, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jung Youn PANG, Shimoji Teruaki, Eun Heay Lee, Seong Min Cho, Chi Seong Kim
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Publication number: 20140069694Abstract: A circuit board includes a circuit pattern formed on a substrate, a first solder resist layer formed on the circuit pattern, an electroless plating layer formed on the circuit pattern on which the first solder resist layer is opened, and a second solder resist layer formed on the first solder resist layer, and a method for manufacturing the same. According to certain embodiments, it is possible to cover a portion which has vulnerable plating quality due to solder resist residue or insufficient wetting around an edge of an existing solder resist layer by including an additional solder resist layer on a surface-treated plating layer. Further, it is possible to protect an undercut portion under the solder resist layer by forming the additional solder resist layer.Type: ApplicationFiled: March 14, 2013Publication date: March 13, 2014Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Seong Min CHO, Eun Heay Iee, Jung Youn Pang, Shimoji Teruaki, Chi Seong Kim
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Publication number: 20130003332Abstract: Disclosed herein are an electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein each of the electroless nickel, palladium, and gold plated coatings has a thickness of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.Type: ApplicationFiled: June 25, 2012Publication date: January 3, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dong Jun Lee, Dong Ju Jeon, Jung Youn Pang, Seong Min Cho, Chi Seong Kim
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Publication number: 20130000960Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a copper pad surface roughness-treated to have a surface roughness of 0.1 to 1.0 ?m pitch period; and an electroless surface treatment plating layer formed on the copper pad. According to the present invention, when the copper pad has a surface roughness of a predetermined pitch period, the electroless surface treatment plating layer formed on the copper pad also has a surface roughness of the predetermined pitch period, thereby having an effect of widening a surface area and improving workability at the time of a wire bonding process for connection with an external device.Type: ApplicationFiled: May 15, 2012Publication date: January 3, 2013Inventors: Dong Jun LEE, Dong Ju Jeon, Jung Youn Pang, Seong Min Cho, Chi Seong Kim
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Publication number: 20100006446Abstract: A method for manufacturing a printed circuit board with an inner via hole, the method including applying a first current to both surfaces of a core layer having the inner via hole, so that a first plating layer grows centerwardly in an equal rate from all the directions of an inner wall of the inner via hole to close one entrance of the inner via hole, leaving a remaining space the inner via hole unfilled; and applying a second current to fill the remaining space of the inner via hole. Also, the manufacturing method does not require filling an inner via hole with an insulating ink, and forming a conductive layer on the insulating ink. Therefore, the method increases productive capacity and reduces manufacturing cost by simplifying the manufacturing process and reducing the lead time.Type: ApplicationFiled: September 17, 2009Publication date: January 14, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Chi-Seong Kim, Hyo-Seung Nam, Seok-Hwan Ahn, Kwang-Ok Jeong, Kyung-Hwan Ko
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Patent number: 7562447Abstract: Disclosed is a method of manufacturing a printed circuit board for fine circuit formation, in which an unnecessary metal layer formed on the upper portion of a circuit pattern is removed through mechanical polishing and then chemical etching. In place of expensive chemical mechanical polishing, in the method of the invention, mechanical polishing and chemical etching are continuously applied to thus sequentially remove and planarize the unnecessary metal layer. Thereby, through an inexpensive, simple, and continuous process, the planarization procedure can be precisely performed, thus making it possible to apply the method to large areas and economically realize a fine circuit pattern.Type: GrantFiled: March 27, 2007Date of Patent: July 21, 2009Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Choon Keun Lee, Seung Hyun Ra, Sang Moon Lee, Jung Woo Lee, Jeong Bok Kwak, Jae Choon Cho, Chi Seong Kim
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Publication number: 20070264755Abstract: Disclosed is a method of manufacturing a printed circuit board for fine circuit formation, in which an unnecessary metal layer formed on the upper portion of a circuit pattern is removed through mechanical polishing and then chemical etching. In place of expensive chemical mechanical polishing, in the method of the invention, mechanical polishing and chemical etching are continuously applied to thus sequentially remove and planarize the unnecessary metal layer. Thereby, through an inexpensive, simple, and continuous process, the planarization procedure can be precisely performed, thus making it possible to apply the method to large areas and economically realize a fine circuit pattern.Type: ApplicationFiled: March 27, 2007Publication date: November 15, 2007Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Choon Keun Lee, Seung Hyun Ra, Sang Moon Lee, Jung Woo Lee, Jeong Bok Kwak, Jae Choon Cho, Chi Seong Kim