Abstract: A memory control system includes a front-end circuitry, a back-end circuitry, and a traffic scheduling circuitry. The front-end circuitry is configured to receive a plurality of access requests from a plurality of devices, and adjust an order of the plurality of devices to access a memory according to a plurality of control signals. The traffic scheduling circuitry is configured to generate a plurality of traffic data based on the plurality of access requests and analyze the plurality of traffic data based on a neural network model and a predetermined rule, in order to determine the plurality of control signals. The back-end circuitry is configured to adjust a task schedule of the memory according to the plurality of control signals.

Abstract: A method for data transmission control of inter field programmable gate array (FPGA) and an associated apparatus are provided. The method includes: utilizing a first register device to latch a set of data from a first FPGA according to a first clock, wherein the set of data is arranged and divided into multiple sets of partial data according to attributes of payloads and pointers; utilizing a time-division multiplexing (TDM) interface to transmit the multiple sets of partial data from the first register device to a second register device according to a TDM clock at multiple time points, respectively; and utilizing the second register device to sequentially receive the multiple sets of partial data, in order to output the set of data to a second FPGA, wherein the second FPGA operates according to a second clock different from the first clock.

Abstract: A method for data transmission control of inter field programmable gate array (FPGA) and an associated apparatus are provided. The method includes: utilizing a first register device to latch a set of data from a first FPGA according to a first clock, wherein the set of data is arranged and divided into multiple sets of partial data according to attributes of payloads and pointers; utilizing a time-division multiplexing (TDM) interface to transmit the multiple sets of partial data from the first register device to a second register device according to a TDM clock at multiple time points, respectively; and utilizing the second register device to sequentially receive the multiple sets of partial data, in order to output the set of data to a second FPGA, wherein the second FPGA operates according to a second clock different from the first clock.

Abstract: A method and a system for controlling data response with the aid of at least one attribute of a transaction identifier (ID) are provided. The method includes: transmitting the at least one attribute in conjunction with the transaction ID from any master device within one or more master devices to a slave device; and according to the at least one attribute, determining whether to utilize a specific data path among multiple data paths for sending response data corresponding to the transaction ID from a memory device within the slave device to the aforementioned master device. More particularly, the specific data path is a data path having maximum transmission efficiency among the multiple data paths.

Abstract: A method and a system for controlling data response with the aid of at least one attribute of a transaction identifier (ID) are provided. The method includes: transmitting the at least one attribute in conjunction with the transaction ID from any master device within one or more master devices to a slave device; and according to the at least one attribute, determining whether to utilize a specific data path among multiple data paths for sending response data corresponding to the transaction ID from a memory device within the slave device to the aforementioned master device. More particularly, the specific data path is a data path having maximum transmission efficiency among the multiple data paths.

Abstract: A processor includes a plurality of storage modules and an arbiter, where the storage modules are arranged for storing a plurality of read/write commands, respectively, and the read/write commands are arranged to read/write a memory external to the processor; and the arbiter is coupled to the storage modules, and is arranged to receive the read/write commands from the storage modules, and arrange a sequence of the read/write commands for transmitting to a memory controller.

Abstract: A processor includes a plurality of storage modules and an arbiter, where the storage modules are arranged for storing a plurality of read/write commands, respectively, and the read/write commands are arranged to read/write a memory external to the processor; and the arbiter is coupled to the storage modules, and is arranged to receive the read/write commands from the storage modules, and arrange a sequence of the read/write commands for transmitting to a memory controller.

Abstract: A network system with QoS management and an associated management method are provided. The network system comprises a switch network, a target device, and at least a source device for issuing a packet to the target device via the switch network. The switch network comprises a flow control unit, a switch unit and a scheduling unit. The flow control unit determines whether to output a high priority packet according to a target priority level and a high priority bandwidth quota of the source device, and directly outputs a low priority packet. The switch unit determines a packet forwarding sequence according to a packet arbitration policy. The scheduling unit determines the sequence for packets to enter the target device. The scheduling unit updates the target priority level as the priority level of a packet entering the target device, and informs the flow control unit of the updated target priority level.

Abstract: A network system with QoS management and an associated management method are provided. The network system comprises a switch network, a target device, and at least a source device for issuing a packet to the target device via the switch network. The switch network comprises a flow control unit, a switch unit and a scheduling unit. The flow control unit determines whether to output a high priority packet according to a target priority level and a high priority bandwidth quota of the source device, and directly outputs a low priority packet. The switch unit determines a packet forwarding sequence according to a packet arbitration policy. The scheduling unit determines the sequence for packets to enter the target device. The scheduling unit updates the target priority level as the priority level of a packet entering the target device, and informs the flow control unit of the updated target priority level.

Abstract: A non-blocked network system and a packet arbitration method thereof are provided to dynamically adjust packet arbitration policy, thereby avoiding the congestion of packet traffic. The non-blocked network system includes a switch network, a source device and a target device. The switch network includes at least a first switch unit and a second switch unit. A first path and a second path connect between the first and second switch units. The target device is coupled to the second switch unit, and the source device is coupled to the first switch unit. Before issuing a first packet to the target device via the first path, the source device issues a corresponding token of the first packet to the second switch unit via the second path, so as to inform the second switch unit that the first packet will pass the first path soon.