Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.

Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: The present disclosure provides a three-phase AC/DC converter aiming for low input current harmonic. The converter includes an input stage for receiving a three-phase AC input voltage, an output stage for at least one load, and one or more switching conversion stages, each stage including a plurality of half bridge modules. The switches in each module operate with a substantially fixed 50% duty cycle and are connected in a specific pattern to couple a DC-link and a neutral node of the input voltage. The AC/DC converter further includes one or more controllers adapted to vary the switching frequency of the switches in the switching conversion stages based on at least one of load voltage, load current, input voltage, and DC-link voltage. The converter can also include one or more decoupling stages, such as, inductive components adapted to decouple the output stage from the switching conversion stages.

Abstract: A system for a semiconductor fabrication facility comprises a transporting tool configured to move a carrier, a first manufacturing tool configured to accept the carrier facing in a first direction, a second manufacturing tool configured to accept the carrier facing in the second direction, and an orientation tool. The carrier is moved to the orientation tool by the transporting tool prior to being moved to the first manufacturing tool or the second manufacturing tool by the transporting tool. The orientation tool rotates the carrier so that the carrier is accepted by the first manufacturing tool or the second manufacturing tool. The transporting tool, the first manufacturing tool, the second manufacturing tool and the orientation tool are physically separated from each other.

Abstract: Example camera and hub arrangements are presented herein. An example device includes an Ethernet connector configured to provide power and data, a camera port configured to provide power and data to a camera module, and an audio port configured to provide power and data to at least one audio input/output module. The device also includes a processor configured to determine one or more camera parameters for the camera module attached to the camera port, such as a type of a camera module attached to the camera port. The device can change operation mode based on camera parameters and audio parameters associated with connected camera modules and audio modules. Different modules can be connected to the device and located remotely from the device.

Abstract: A package device preventing solder overflow provides a space or structure to limit the location of the solder when dispensing the solder. The package device includes a die, an anti-overflow layer, a first pin, a second pin, and a package body. The die has an electrode pad. The anti-overflow layer is disposed on a top surface of the electrode pad and has an opening to expose the top surface of the electrode pad. The first pin is connected to the die. The second pin is soldered to the electrode pad of the die through the opening of the anti-overflow layer. The package body covers the die.

Abstract: A microscopic observation method configured to observe a specimen in a specimen carrier that includes the following steps: placing the specimen carrier at an observation point; obtaining a length of the specimen carrier along a movement direction, a thickness of the specimen carrier along an observation direction of a microscope objective, an observation angle of the microscope objective, and a relative distance between a lateral surface of the specimen carrier and the microscope objective along the movement direction; and adjusting an incident angle of a light beam emitted from a dark-field illumination towards the specimen carrier according to a calculation result of the length, the thickness, the observation angle, and the relative distance.

Abstract: A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region comprises a well layer and a barrier layer, wherein the barrier layer has a band gap; a first electron blocking layer between the second semiconductor structure and the active region, wherein the first electron blocking layer comprises a band gap which is greater than the band gap of the barrier layer; a first aluminum-containing layer between the first electron blocking layer and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; a confinement layer between the first aluminum-containing layer and the active region; and a second aluminum-containing layer between the second semiconductor structure and the first electron blocking layer; wherein both the first alumi

Abstract: An OCT scanning probe includes a tubular housing, at least one electrode, an optical fiber scanner and an auxiliary localization component. The electrode is disposed on an outer surface of the tubular housing. The optical fiber scanner is disposed in the tubular housing and includes an optical fiber and an optical element. The optical element is disposed on an emitting end of the optical fiber and at corresponding position to a light transmittable portion of the tubular housing. The auxiliary localization component is disposed on the tubular housing, and overlaps part of the light transmittable portion. A light beam emitted from the optical fiber scanner passes through the light transmittable portion to obtain a tomographic image. An interaction of the light beam with the auxiliary localization component causes a characteristic in the tomographic image, with the characteristic corresponding to the auxiliary localization component.

Abstract: A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region includes multiple alternating well layers and barrier layers, wherein each of the barrier layers has a band gap, the active region further includes an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region, wherein the electron blocking region includes a band gap, and the band gap of the electron blocking region is greater than the band gap of one of the barrier layers; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the electron blocking region; a confinement layer between the fi

Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region comprises multiple alternating well layers and first barrier layers, wherein each of the first barrier layers has a band gap, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; a first electron blocking layer between the second semiconductor structure and the active region, wherein the first electron blocking layer having a band gap greater than the band gap of one of the first barrier layers; a first aluminum-containing layer between the first electron blocking layer and the active region, wherein the first aluminum-containing layer has a first thickness and a band gap greater than the band gap of the first electron blocking layer; and a second aluminum-conta

Abstract: An optical probe includes a cylindrical lens adapted to receive and transmit incident light. A light-emitting surface of the cylindrical lens is a curved end surface having a concentric ring-shaped diffractive microstructure. A working position of the optical probe is a position where a diffraction order is 1 when the incident light having a design wavelength between a first wavelength and a second wavelength passes through the diffractive microstructure. When passing through the cylindrical lens, the incident light having the first wavelength produces a diffraction effect with the diffractive microstructure and is converged at a first wavelength working position approximately the same as the working position of the optical probe with the diffraction order of 1. After being refracted by the curved end surface, the incident light having the second wavelength is converged at a second wavelength working position approximately the same as the working position of the optical probe.

Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.

Abstract: An optical fiber scanning probe includes a rotor and at least one optical fiber. The rotor includes a torque rope rotatable about its central axis. The optical fiber is disposed on the rotor and eccentric relative to the torque rope. A central axis of the optical fiber is substantially parallel to the central axis of the torque rope. When the torque rope rotates about its central axis, the rotor brings a free end of the optical fiber to scan along an arc path.

Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Abstract: An ultrasonic sensing device includes a housing, a piezoelectric assembly, a board and a plurality of fixing members. The housing includes a bottom wall, a top wall and a surrounding side wall connected between the top wall and the bottom wall. The piezoelectric assembly includes an encapsulating body and a piezoelectric sheet, wherein at least a portion of the piezoelectric sheet is enclosed by the encapsulating body and has a sensing surface exposed to the encapsulating body and facing the bottom wall. The board is disposed on the top wall of the housing and has a pressing surface facing the encapsulating body and the top wall. The plurality of fixing members is configured to fix the board to the top wall of the housing to press the board to the encapsulating body of the piezoelectric assembly, thereby pressing the sensing surface of the piezoelectric sheet to the bottom wall.