Patents by Inventor Chi-Shen Ho

Chi-Shen Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer level mounting frame for ball grid array packaging, and method of making and using the same
    Patent number: 7208344
    Abstract: A method of forming a semiconductor package including placing a semiconductor chip in cavities of a semiconductor chip carrier substrate.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: April 24, 2007
    Assignee: Aptos Corporation
    Inventor: Chi Shen Ho
  • Flexible multi-chip module and method of making the same
    Patent number: 7141875
    Abstract: A semiconductor package including a flexible multichip module having multiple chips on flexible appendages with the flexible appendages folded so that the semiconductor chips are arranged in aligned and stacked positions.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: November 28, 2006
    Assignee: Aptos Corp
    Inventors: Min Chih Hsuan, Chi Shen Ho, Chang-Ming Lin, Kuolung Lei
  • Wafer scale integration packaging and method of making and using the same
    Patent number: 7078272
    Abstract: A method of making a microelectronic device comprising: making a device B comprising providing a structure having a first bond pad, depositing a first electrically conductive material having a first reflow temperature over the first bond pad, and depositing a second electrically conductive material having a second reflow temperature over the first electrically conductive material, and wherein the second reflow temperature is less than the first reflow temperature, and heating the device to a temperature sufficient to reflow the second electrically conductive material but not the first electrically conductive material so that the second electrically conductive material encapsulates the first electrically conductive material to provide a first bump for making electrical connection to device B.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: July 18, 2006
    Assignee: Aptos Corporation
    Inventors: Chi-Shen Ho, Chang-Ming Lin
  • Wafer scale integration packaging and method of making and using the same
    Publication number: 20060063311
    Abstract: A method of making a microelectronic device comprising: making a device B comprising providing a structure having a first bond pad, depositing a first electrically conductive material having a first reflow temperature over the first bond pad, and depositing a second electrically conductive material having a second reflow temperature over the first electrically conductive material, and wherein the second reflow temperature is less than the first reflow temperature, and heating the device to a temperature sufficient to reflow the second electrically conductive material but not the first electrically conductive material so that the second electrically conductive material encapsulates the first electrically conductive material to provide a first bump for making electrical connection to device B.
    Type: Application
    Filed: September 20, 2004
    Publication date: March 23, 2006
    Inventors: Chi-Shen Ho, Chang-Ming Lin
  • Wafer level mounting frame with passive components integration for ball grid array packaging
    Publication number: 20060001145
    Abstract: A mounting frame substrate having a cavity formed therein and a semiconductor chip in the cavity of the substrate. The semiconductor chip includes bond pads along the periphery thereof and forming a redistribution trace connected to a bond pad of the chip.
    Type: Application
    Filed: July 3, 2004
    Publication date: January 5, 2006
    Inventors: Chi-Shen Ho, Chang-Ming Lin
  • Flexible multi-chip module and method of making the same
    Publication number: 20050227412
    Abstract: A semiconductor package including a flexible multichip module having multiple chips on flexible appendages with the flexible appendages folded so that the semiconductor chips are arranged in aligned and stacked positions.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Min Chih Hsuan, Chi Shen Ho, Chang-Ming Lin, Kuolung Lei