Patents by Inventor Chi-Shen Lo

Chi-Shen Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7196006
    Abstract: A method of manufacturing a microelectronic device, including performing a first inspection of a device feature during an intermediate stage of manufacture, cleaning the device feature after the first inspection, and performing a second inspection of the device feature after cleaning the device feature.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: March 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pey-Yuan Lee, Feng-Liang Lai, Cheng-Kuo Chu, Chi-Shen Lo
  • Publication number: 20050224995
    Abstract: A method of manufacturing a microelectronic device, including performing a first inspection of a device feature during an intermediate stage of manufacture, cleaning the device feature after the first inspection, and performing a second inspection of the device feature after cleaning the device feature.
    Type: Application
    Filed: April 13, 2004
    Publication date: October 13, 2005
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pey-Yuan Lee, Feng-Liang Lai, Cheng-Kuo Chu, Chi-Shen Lo
  • Patent number: 6862545
    Abstract: A method for calibrating a linewidth measurement tool and a system for calibrating the linewidth measurement tool each employ a correction of a series of periodic actual measurements of at least one single measurement location of a topographic feature within a linewidth standard with an exponentially weighted moving average of a series of deviations of the series of periodic actual measurements from a corresponding series of regressed data points derived from mathematical regression of the series of periodic actual measurements. Such a correction provides for a more accurate calibration of the linewidth measurement tool and a more accurate measurement of linewidths within microelectronic products while employing the calibrated linewidth measurement tool.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: March 1, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Pey-Yuan Lee, Hong-Ji Yang, Yi-Hung Chen, Chi-Shen Lo, Chen-Ning Fuh, Wen-Chung Lee
  • Patent number: 6710889
    Abstract: A method for measuring a dielectric layer thickness calibration reference standard including providing a substrate having a dielectric layer for calibrating a dielectric layer thickness measuring tool; cleaning the dielectric layer according to a cleaning process including at least one of spraying and scrubbing; and, measuring the thickness of the dielectric layer with the dielectric layer thickness measuring tool including at least one portion of the dielectric layer displaced from the substrate center.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: March 23, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Pey-Yuan Lee, Chi-Shen Lo, Sian-Ren Horng, Han-Liang Tseng, Wei-Ming You, Yi-Hung Chen
  • Publication number: 20040004730
    Abstract: A method for measuring a dielectric layer thickness calibration reference standard including providing a substrate having a dielectric layer for calibrating a dielectric layer thickness measuring tool; cleaning the dielectric layer according to a cleaning process including at least one of spraying and scrubbing; and, measuring the thickness of the dielectric layer with the dielectric layer thickness measuring tool including at least one portion of the dielectric layer displaced from the substrate center.
    Type: Application
    Filed: July 2, 2002
    Publication date: January 8, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pey-Yuan Lee, Chi-Shen Lo, Shean-Ren Horng, Han-Liang Tseng, Wei-Ming You, Yi-Hung Chen
  • Patent number: 6485576
    Abstract: The present invention provides a method for removing a coating layer of SOG or photoresist from a wafer flat side on a wafer by first injecting a flow of a cleaning solution at the bottom surface of the wafer at a location adjacent to the edge of the wafer, and then rotating the wafer at a rotational speed sufficiently high so as to cause the cleaning solution being pulled from the bottom side to the top side of the wafer by flowing around the edge to remove the coating layer covering the unintended area on the top surface of the wafer.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: November 26, 2002
    Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Chi Huang, Chi-Shen Lo
  • Patent number: 5783097
    Abstract: A simple, non critical, low cost process step is added to the manufacture of integrated circuit wafers to remove a ridge of dielectric material remaining at the flat edge of the wafer after an edge rinse has removed the ridge of dielectric from the circular edges of the wafer. A layer of dielectric, such as Spin-On-Glass or the like, is formed on the wafer. An edge rinse is then used to remove the ridge of dielectric formed at the wafer edge, however the edge rinse does not remove the ridge of dielectric at the flat edge of the wafer. A layer of photoresist is formed on the wafer, selectively exposed, and developed to form a photoresist mask. The flat edge of the wafer is then dipped in buffered oxide etch to remove the dielectric material at the flat edge of the wafer. The photoresist mask is then stripped and processing of the wafer is continued.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: July 21, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Shen Lo, Chao-Hsin Chang, Chia-Hsiang Chen, Hsien-Wen Chang, Chih-Heng Shen
  • Patent number: D342174
    Type: Grant
    Filed: October 28, 1992
    Date of Patent: December 14, 1993
    Inventor: Chi-Shen Lo