Patents by Inventor Chi-Sheng Liao

Chi-Sheng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10732495
    Abstract: An illumination system includes a coherent light source, a first light-combining device, an optical wavelength conversion module, and a first auxiliary light source. The coherent light source emits a coherent light beam. The first light-combining device is disposed on a transmission path of the coherent light beam. The light wavelength conversion module is disposed on a transmission path of the coherent light beam transmitted from the first light-combining device and converts the coherent light beam into a first converted light beam, and reflects the first converted light beam back to the first light-combining device. The first auxiliary light source emits a first auxiliary light beam which is transmitted to the first light-combining device. The first light-combining device combines the first auxiliary light beam and the first converted light beam. A projection apparatus and a method for driving the illumination system are also provided.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 4, 2020
    Assignee: Coretronic Corporation
    Inventors: Chi-Tang Hsieh, Ko-Shun Chen, Chi-Hsun Wang, Hao-Wei Chiu, Hou-Sheng Wang, Chien-Chung Liao, Yin-Cheng Lin, De-Sheng Yang, Ming-Tsung Weng
  • Publication number: 20200150546
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi CHUNG, Yung-Cheng CHEN, Fei-Gwo TSAI, Chi-Hung LIAO, Shih-Chi FU, Wei-Ti HSU, Jui-Ping CHUANG, Tzong-Sheng CHANG, Kuei-Shun CHEN, Meng-Wei CHEN
  • Patent number: 10644701
    Abstract: An input output circuit and a self-biased circuit are provided. The self-biased circuit includes a tracking circuit, a biasing control circuit and first to fourth transistors. The tracking circuit receives a first power voltage, and generates a bias voltage according to variation of the first power voltage. The biasing control circuit generates a first control signal, a second control signal and a third control signal according to the first power voltage and a voltage on a pad. The first transistor is coupled to the pad and controlled by the first control signal. The second transistor is controlled by the second control signal to provide a bias voltage. The third transistor is coupled to the pad and controlled by the third control signal and generates a fourth control signal according to the voltage on the pad. The fourth transistor is controlled by the fourth control signal to generate the bias voltage.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 5, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Huang-Shiang Su, Chi-Sheng Liao, Jeng-Huang Wu
  • Patent number: 10634706
    Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Tang-Long Chang, Chi-Sheng Liao, Jeng-Huang Wu
  • Publication number: 20200113454
    Abstract: A vibration sensing device includes a piezoelectric element, a static force meter, a vibration conduction element and a casing. The piezoelectric element is provided for converting vibration into an electronic signal. The static force meter is provided for converting static force into an electronic signal. The vibration conduction element is provided for vibration to the piezoelectric element. The piezoelectric element, the static force meter, and the vibration conduction element are covered by the casing.
    Type: Application
    Filed: May 21, 2019
    Publication date: April 16, 2020
    Applicant: Hong Yue Technology Corporation
    Inventors: Chi-Sheng Wu, Mei-Hua Liao
  • Patent number: 10591708
    Abstract: A slit illumination device includes a first light-emitting element, a first diaphragm and a projection lens group. The first light-emitting element generates a primary illumination light. The first diaphragm has at least one opening and is disposed on a light exit side of the first light-emitting element, wherein the opening is an elongate shaped opening. The projection lens group is disposed on a light exit side of the first diaphragm, converging the primary illumination light and projecting it to a target object. A distance from the first diaphragm to the projection lens group is 1-2 times a focal length of the projection lens group on a light entrance side. The foregoing slit illumination device has advantages of simple structure, small size, and longer depth of field. A microscope system including the foregoing slit illumination device is also disclosed.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: March 17, 2020
    Assignee: MEDIMAGING INTEGRATED SOLUTION, INC.
    Inventors: Chu-Ming Cheng, Long-Sheng Liao, Chi-Yuan Kang, Ming-Hsien Hsieh
  • Publication number: 20200035670
    Abstract: A electrostatic discharge (ESD) protection apparatus for an integrated circuit (IC) is provided. A first electrostatic current rail and a second electrostatic current rail of the ESD protection apparatus do not directly connected to any bonding pad of the IC. The ESD protection apparatus further includes a clamp circuit and four ESD protection circuits. The clamp circuit is coupled between the first electrostatic current rail and the second electrostatic current rail. A first ESD protection circuit is coupled between the first electrostatic current rail and a signal pad of the IC. A second ESD protection circuit is coupled between the signal pad and the second electrostatic current rail. A third ESD protection circuit is coupled between a first power rail and the second electrostatic current rail. A fourth ESD protection circuit is coupled between the second electrostatic current rail and a second power rail.
    Type: Application
    Filed: October 8, 2018
    Publication date: January 30, 2020
    Applicant: Faraday Technology Corp.
    Inventors: Chia-Ku Tsai, Chi-Sheng Liao, Jeng-Huang Wu
  • Patent number: 10534272
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Publication number: 20190204368
    Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.
    Type: Application
    Filed: April 9, 2018
    Publication date: July 4, 2019
    Inventors: Tang-Long Chang, Chi-Sheng Liao, Jeng-Huang Wu
  • Patent number: 9673808
    Abstract: A power-on-reset circuit including a first diode-connected transistor, a second diode-connected transistor, a resistor and a current comparator circuit is provided. A cathode of the first diode-connected transistor is coupled to a reference voltage. A first end of the resistor is coupled to a power voltage. A second end of the resistor is coupled to an anode of the first diode-connected transistor. A cathode of the second diode-connected transistor is coupled to the reference voltage. An anode of the second diode-connected transistor is coupled to the first end of the resistor. The current comparator circuit is coupled to the first diode-connected transistor and the second diode-connected transistor. The current comparator circuit compares a current of the first diode-connected transistor with a current of the second diode-connected transistor to obtain a comparing result, wherein the comparing result determines a reset signal.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 6, 2017
    Assignee: Faraday Technology Corp.
    Inventors: Kai-Neng Tang, Chi-Sheng Liao
  • Patent number: 9537449
    Abstract: A crystal oscillation circuit, a gain stage of the crystal oscillation circuit and a method for designing the same are provided. The gain stage includes multiple amplifiers and multiple current-limiting resistors. Input terminals of the amplifiers are coupled together to a first bonding pad, wherein transconductances of the amplifiers are different from each other. The first bonding pad is used for electrically coupling to a first terminal of an oscillation crystal module. First terminals of the current-limiting resistors are respectively coupled to output terminals of the amplifiers in a one-on-one manner, and second terminals of the current-limiting resistors are coupled together to a second bonding pad, wherein the second bonding pad is used for electrically coupling to a second terminal of the oscillation crystal module.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: January 3, 2017
    Assignee: Faraday Technology Corp.
    Inventors: Wei-Chieh Liao, Chi-Sheng Liao
  • Publication number: 20160373060
    Abstract: A crystal oscillation circuit, a gain stage of the crystal oscillation circuit and a method for designing the same are provided. The gain stage includes multiple amplifiers and multiple current-limiting resistors. Input terminals of the amplifiers are coupled together to a first bonding pad, wherein transconductances of the amplifiers are different from each other. The first bonding pad is used for electrically coupling to a first terminal of an oscillation crystal module. First terminals of the current-limiting resistors are respectively coupled to output terminals of the amplifiers in a one-on-one manner, and second terminals of the current-limiting resistors are coupled together to a second bonding pad, wherein the second bonding pad is used for electrically coupling to a second terminal of the oscillation crystal module.
    Type: Application
    Filed: September 17, 2015
    Publication date: December 22, 2016
    Applicant: Faraday Technology Corp.
    Inventors: Wei-Chieh Liao, Chi-Sheng Liao
  • Publication number: 20160161665
    Abstract: A display device including a heat dissipation component, a display panel, a light guide plate, an optical film set, and a light source set is provided. The heat dissipation component has a supporting surface, a first connecting surface, and a second connecting surface. The supporting surface supports the display panel. The light guide plate is connected to the first connecting surface, and has a light incident surface and a light emitting surface. The optical film set is connected to the second connecting surface, and located between the light guide plate and the display panel, wherein the light emitting surface of the light guide plate faces the optical film set. The light source set is disposed on the heat dissipation component, and aligned to the light incident surface of the light guide plate. A backlight module adapted to the display device is also provided.
    Type: Application
    Filed: July 8, 2015
    Publication date: June 9, 2016
    Inventors: Ching-Hung Chen, Wen-Pin Yang, Chi-Sheng Liao, Chun-Chung Hsiao, Ruei-An Lyu, Hua-Te Feng
  • Patent number: 7826187
    Abstract: A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: November 2, 2010
    Assignees: Himax Technologies Limited, National Chiao-Tung University
    Inventors: Ming-Dou Ker, Cheng-Cheng Yen, Chi-Sheng Liao, Tung-Yang Chen
  • Patent number: D850632
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 4, 2019
    Assignee: SPECIAL PROTECTORS CO., LTD.
    Inventors: Chi-Sheng Chiang, Chi-Lan Liao
  • Patent number: D850633
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 4, 2019
    Assignee: SPECIAL PROTECTORS CO., LTD.
    Inventors: Chi-Sheng Chiang, Chi-Lan Liao
  • Patent number: D850635
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 4, 2019
    Assignee: SPECIAL PROTECTORS CO., LTD.
    Inventors: Chi-Sheng Chiang, Chi-Lan Liao
  • Patent number: D852369
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 25, 2019
    Assignee: SPECIAL PROTECTORS CO., LTD.
    Inventors: Chi-Sheng Chiang, Chi-Lan Liao
  • Patent number: D852966
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: July 2, 2019
    Assignee: SPECIAL PROTECTORS CO., LTD.
    Inventors: Chi-Sheng Chiang, Chi-Lan Liao
  • Patent number: D860466
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: September 17, 2019
    Assignee: SPECIAL PROTECTORS CO., LTD.
    Inventors: Chi-Sheng Chiang, Chi-Lan Liao