Patents by Inventor Chi-Sheng Lo

Chi-Sheng Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6719885
    Abstract: A method of reducing stress induced defects in a substrate according to an HDP-CVD process including providing a substrate for depositing a layer of material according to an HDP-CVD process; igniting a plasma for carrying out an HDP-CVD process; adjusting plasma operating parameters to achieve a first deposition-sputter ratio with respect to the substrate; depositing a first portion of the layer of material according to a first range of substrate temperatures; and, depositing at least a second portion of the layer of material according to at least a second range of substrate temperatures.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: April 13, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chun-Sheng Lin, Jui-Hei Huang, Chi-Sheng Lo, Long-Siang Chuang
  • Publication number: 20030165632
    Abstract: A method of reducing stress induced defects in a substrate according to an HDP-CVD process including providing a substrate for depositing a layer of material according to an HDP-CVD process; igniting a plasma for carrying out an HDP-CVD process; adjusting plasma operating parameters to achieve a first deposition-sputter ratio with respect to the substrate; depositing a first portion of the layer of material according to a first range of substrate temperatures; and, depositing at least a second portion of the layer of material according to at least a second range of substrate temperatures.
    Type: Application
    Filed: March 1, 2002
    Publication date: September 4, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Sheng Lin, Jui-Hei Huang, Chi-Sheng Lo, Long-Siang Chuang