Abstract: A line layout and a spacer self-aligned quadruple patterning method thereof are provided. The line layout includes a first line, a second line, a third line, and a fourth line. The second line and the third line are disposed between the first line and the fourth line. The first line, the second line, the third line, and the fourth line respectively extend in a first direction. An end segment of the second line and an end segment of the third line respectively include a first protrusion portions that extend in a second direction. The first protrusion portion of the end segment of the second line protrudes toward the first line. The first protrusion portion of the end segment of the third line protrudes toward the fourth line.

Abstract: A line layout and a spacer self-aligned quadruple patterning method thereof are provided. The line layout includes a first line, a second line, a third line, and a fourth line. The second line and the third line are disposed between the first line and the fourth line. The first line, the second line, the third line, and the fourth line respectively extend in a first direction. An end segment of the second line and an end segment of the third line respectively include a first protrusion portions that extend in a second direction. The first protrusion portion of the end segment of the second line protrudes toward the first line. The first protrusion portion of the end segment of the third line protrudes toward the fourth line.

Abstract: A method for forming a 3D memory is described. A stacked structure including alternately arranged semiconductor layers and insulating layers is formed on a substrate. The stacked structure is patterned into linear stacks in a row direction, wherein each linear stack includes alternately arranged channel layers and linear insulators. An insulating material is filled in between the linear stacks. Damascene openings are formed in the insulating material between each two neighboring linear stacks, wherein each damascene opening exposes a portion of each of the opposite sidewalls of all the channel layers of two neighboring linear stacks. A charge trapping layer is formed. Word lines are formed in the damascene openings.

Abstract: Provided is a method for fabricating a semiconductor device including the following steps. A silicon-containing conductive layer is formed on a substrate. Then, a dielectric layer is formed around the silicon-containing conductive layer. A portion of the dielectric layer is removed to expose a first sidewall of the silicon-containing conductive layer. A shielding structure is formed on a partial surface of the silicon-containing conductive layer, and the shielding structure exposes at least the first sidewall. A metal layer is formed on the substrate to cover the silicon-containing conductive layer not covered by the shielding structure. A salicide process is performed to form a silicide layer.

Abstract: Provided is a method for fabricating a semiconductor device including the following steps. A silicon-containing conductive layer is formed on a substrate. Then, a dielectric layer is formed around the silicon-containing conductive layer. A portion of the dielectric layer is removed to expose a first sidewall of the silicon-containing conductive layer. A shielding structure is formed on a partial surface of the silicon-containing conductive layer, and the shielding structure exposes at least the first sidewall. A metal layer is formed on the substrate to cover the silicon-containing conductive layer not covered by the shielding structure. A salicide process is performed to form a silicide layer.

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a memory material layer, a first dielectric layer, a first gate layer, a second gate layer, and a source/drain (S/D) region. The substrate has a trench, and the memory material layer is formed on a sidewall of the trench. The first gate layer, the second gate layer, and the first dielectric layer, which is formed between the first gate layer and the second gate layer, are filled in the trench. The source/drain region is formed in the substrate and adjacent to the memory material layer. The first gate layer is extended in a direction perpendicular to a direction in which the source/drain region is extended.

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a memory material layer, a first dielectric layer, a first gate layer, a second gate layer, and a source/drain (S/D) region. The substrate has a trench, and the memory material layer is formed on a sidewall of the trench. The first gate layer, the second gate layer, and the first dielectric layer, which is formed between the first gate layer and the second gate layer, are filled in the trench. The source/drain region is formed in the substrate and adjacent to the memory material layer. The first gate layer is extended in a direction perpendicular to a direction in which the source/drain region is extended.