Patents by Inventor Chi-Shi Chen

Chi-Shi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8399303
    Abstract: The present invention provides a method for manufacturing a modularized integrated circuit (IC). The method includes the following steps: providing a base; and coupling an input/output module with the base. The base includes a lead-frame and a first package. The first package covers the lead-frame but exposes first contact points. The input/output module includes a first substrate, a plurality of first conducting columns, and a plurality of third contact points. A portion of each of the third contact points is electrically connected to a corresponding one of the first contact points. The method enhances the flexibility of IC design, and reduces the time and costs of developing new process techniques.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: March 19, 2013
    Assignee: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Chi-Sheng Lin, Chi-Shi Chen, Chien-Ming Wu
  • Patent number: 8274794
    Abstract: A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: September 25, 2012
    Assignee: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Chin-Long Wey, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chi-Shi Chen, Chi-Sheng Lin
  • Patent number: 8199510
    Abstract: A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: June 12, 2012
    Assignees: National Chip Implementation Center, National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chin-Long Wey, Chi-Shi Chen, Chi-Sheng Lin
  • Publication number: 20110188210
    Abstract: A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.
    Type: Application
    Filed: April 1, 2010
    Publication date: August 4, 2011
    Applicant: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Chin-Long Wey, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chi-Shi Chen, Chi-Sheng Lin
  • Publication number: 20110096506
    Abstract: A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.
    Type: Application
    Filed: January 12, 2010
    Publication date: April 28, 2011
    Applicant: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chin-Long Wey, Chi-Shi Chen, Chi-Sheng Lin
  • Publication number: 20100330741
    Abstract: A fabrication method for a system-on-chip (SoC) module is provided. The fabrication method includes the steps of providing at least two SoC sub-modules and connecting the SoC sub-modules. The SoC sub-modules are electrically connected with each other by connection interfaces of the SoC sub-modules so as to form the SoC module. As the SoC sub-modules have been verified in advance, the time required for verifying the resulting SoC module can be significantly reduced. As for application-specific SoC modules, they are fabricated by connecting with application-specific SoC sub-modules via the appropriate connection interfaces. Thus, the time and costs for developing SoC modules can both be minimized.
    Type: Application
    Filed: September 30, 2009
    Publication date: December 30, 2010
    Applicant: National Chip Implementation Center National Applied Research Laboratories.
    Inventors: Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chin-Long Wey, Chi-Shi Chen, Chi-Sheng Lin