Abstract: A method and device to track navigational satellite signals, are claimed. In this invention, a combination of down-sampling and frequency domain transformation are used to track the navigational satellite signals under dynamic environment. A Fast Fourier Transform (FFT) with long coherent integration has been employed to determine the varying frequency components with high resolution. By representing a number of correlation values with their average value, it is possible to represent a long sequence of input values by a smaller number of values and a relatively short length FFT can reveal the low frequency components that are present in the signal during tracking operation. A large reduction in the computational load may be achieved using this down-sampling method without compromising on the frequency resolution.

Abstract: A method and device to acquire navigational satellite signals combines non-coherent and coherent integrations and can efficiently acquire both strong and weak signals. Successive steps eliminate lower powered and less likely combinations of code offsets and carrier frequencies or dwells of a given satellite signal. Only remaining dwells then are correlated and integrated over larger time duration to obtain the most probable dwell or dwells, which results in reduced computational load. The selection of most likely dwells is based on Parseval's theorem on equivalence of power in time and frequency domains. An optimal estimator algorithm efficiently estimates the probable navigation data bits embedded in the received signal. In case of an ambiguity due to several possible dwells, the steps are repeated with a new set of signal samples.

Abstract: A method and device to acquire navigational satellite signals combines non-coherent and coherent integrations and can efficiently acquire both strong and weak signals. Successive steps eliminate lower powered and less likely combinations of code offsets and carrier frequencies or dwells of a given satellite signal. Only remaining dwells then are correlated and integrated over larger time duration to obtain the most probable dwell or dwells, which results in reduced computational load. The selection of most likely dwells is based on Parseval's theorem on equivalence of power in time and frequency domains. An optimal estimator algorithm efficiently estimates the probable navigation data bits embedded in the received signal. In case of an ambiguity due to several possible dwells, the steps are repeated with a new set of signal samples.

Abstract: The invention provides a method and apparatus to optimally estimate and adaptively compensate the temperature-induced frequency drift of a crystal oscillator in a navigational signal receiver. A Read-Write memory encodes two tables, one for looking up frequency drift values versus temperature readings and another one for valid data confirmation on the first table. The initially empty look-up table is gradually populated with frequency drift values while the receiver computes the frequency drift along with its position. During initial start of the receiver or re-acquisition of satellite signals, the stored frequency drift value corresponding to the current temperature is used. If no valid frequency drift value is available, the frequency drift value is computed based on the existing frequency drift values in the table. This invention reduces the Time-To-First-Fix (TTFF) of the receiver and enables the receiver to self-calibrate, thus no additional factory calibration would be necessary.

Abstract: The present invention provides a new baseband integrated circuit (IC) architecture for direct sequence spread spectrum (DSSS) communication receivers. The baseband IC has a single set of baseband correlators serving all channels in succession. No complex parallel channel hardware is required. A single on-chip code Numerically Controlled Oscillator (NCO) drives a pseudorandom number (PN) sequence generator, generates all code sampling frequencies, and is capable of self-correct through feedback from an off-chip processor. A carrier NCO generates corrected local frequencies. These on-chip NCOs generate all the necessary clocks. This architecture advantageously reduces the total hardware necessary for the receiver and the baseband IC thus can be realized with a minimal number of gate count. The invention can accommodate any number of channels in a navigational system such as the Global Positioning System (GPS), GLONASS, WAAS, LAAS, etc.

Abstract: The present invention provides a method and apparatus for a satellite navigation receiver to lock onto satellite signals in the cold start mode with no information on the receiver position, the satellite position, or time estimates stored in the receiver's memory. All satellites in a positioning system are divided into groups based on the satellite constellation structure. In an embodiment, the positioning system is the Global Positioning System (GPS) and all GPS satellites are divided into three groups. During initialization of the receiver, the satellites are searched per group to lock onto at least one satellite signal. Other satellites are then searched in a given order based on their respective distance or proximity to the first satellite acquired. This method reduces the Time-to-First-Fix (TTFF) ordinarily required by conventional receivers in the cold start mode.

Abstract: An apparatus for multiplying and accumulating numeric quantities, including a multiplier for receiving the numeric quantities, with the multiplier having a sum output and a carry output. A first shift register has an input coupled to the sum output of the multiplier, and a second shift register has an input coupled to the carry output of the multiplier. An adder and third shift register are used to complete processing of the apparatus' arithmetic operations.

Abstract: A programmable motion estimator includes one dual ported memory for storing an image block, the prediction error, and a temporary block used in interpolation, and a pixel-group random access dual ported memory for storing a search window. The two ports of the two memories are selectively applied to an arithmetic logic unit, or ALU, through a multiplexer. One output of the ALU provides an absolute difference, which is furnished to a tree adder. Another output of the ALU provides an average value or a difference value, as selected, which is routed to the inputs of the image memory and the search memory. In motion vector searching, the ALU performs pixel absolute difference arithmetic using the pixel groups from the image memory and from the search memory, and determines a sum of absolute differences in the tree adder. In half pixel interpolation, the ALU performs pixel averaging arithmetic using pixel groups from the search memory, and writes back to the search memory.

Abstract: A vision processor includes a control section, a motion estimation section, and a discrete cosine transform (“DCT”) section. The motion estimation section includes two memories, an image memory with two read ports and a write port, and a search memory with two read ports and a write port. The DCT section includes a DCT memory configurable as a two read, two write port memory and as a four read, four write port memory. The ports of these memories are selectively applied to various elements in the motion estimation path and the DCT path. In motion vector searching, the ALU performs averaging and difference operations on pixels in the frame and search memories. Data from the search memory is shifted for certain operations, before arithmetic operations in the ALU are performed.

Abstract: An improved image sensing array including a semiconductive substrate having formed therein an array of discrete substrate areas organized in rows and columns. The array of areas is segmented into a plurality of blocks, each including a sub-array of the areas. At least one of the rows of each block has at least one reader cell formed therein, and the remaining rows of the block have photosensor cells formed in each area thereof. Each column of each block forms a column block including a plurality of photosensor cells, and a node line communicatively coupling each photosensor cell of the column block to an associated reader cell. A row address line is coupled to each photosensor cell in a particular row of the array. A column bit line is coupled to each reader cell in a particular column of the array. A block select line is coupled to each reader cell in a particular row of the array containing reader cells.

Abstract: According to one embodiment, a cost-effective videophone communicates over a POTS line, and generates video data in a format for a selected display type. The device includes a video source to capture images and to generate video data representing the images; a telephone line interface circuit, including a signal transmission circuit and a signal receiver circuit; to transmit and receive video data over the telephone line; a memory circuit for storing a main program including video data processing consistent with at least one video-coding recommendation and for processing pixels for a certain display type; a programmable processor circuit for executing the code for processing pixels for a certain display type and, in response, causing image data to be output for display. The programmable processor circuit has a DSP section for compressing and decompressing video, and a RISC-type processor section for general control.

Abstract: A programmable motion estimator includes one dual ported memory for storing an image block, the prediction error, and a temporary block used in interpolation, and a pixel-group random access dual ported memory for storing a search window. The two ports of the two memories are selectively applied to an arithmetic logic unit, or ALU, through a multiplexer. One output of the ALU provides an absolute difference, which is furnished to a tree adder. Another output of the ALU provides an average value or a difference value, as selected, which is routed to the inputs of the image memory and the search memory. In motion vector searching, the ALU performs pixel absolute difference arithmetic using the pixel groups from the image memory and from the search memory, and determines a sum of absolute differences in the tree adder. In half pixel interpolation, the ALU performs pixel averaging arithmetic using pixel groups from the search memory, and writes back to the search memory.

Abstract: A programmable motion estimator includes one dual ported memory for storing an image block, the prediction error, and a temporary block used in interpolation, and a pixel-group random access dual ported memory for storing a search window. The two ports of the two memories are selectively applied to an arithmetic logic unit, or ALU, through a multiplexer. One output of the ALU provides an absolute difference, which is furnished to a tree adder. Another output of the ALU provides an average value or a difference value, as selected, which is routed to the inputs of the image memory and the search memory. Among other tasks, the programmable motion estimator performs motion vector searching, half pixel interpolation, quarter pixel interpolation and error prediction determination.

Abstract: A vision processor includes a control section, a motion estimation section, and a discrete cosine transform ("DCT") section. The motion estimation section includes two memories, an image memory with two read ports and a write port, and a search memory with two read ports and a write port. The DCT section includes a DCT memory configurable as a two read, two write port memory and as a four read, four write port memory. The ports of these memories are selectively applied to various elements in the motion estimation path and the DCT path. In motion vector searching, the ALU performs averaging and difference operations on pixels in the frame and search memories. Data from the search memory is shifted for certain operations, before arithmetic operations in the ALU are performed.

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract: CCDs and bipolar transistors are formed together on a silicon chip. For n channel CCDs and npn transistors, only a single extra diffusion is necessary in addition to the diffusions used for the CCDs alone. This step is diffusion of n.sup.+ collector wells, and is performed before CCD channel stop-transistor base diffusion. For p channel CCDs and pnp transistors, two extra diffusions are necessary and are: diffusion of a p collector wells, and diffusion of n.sup.+ base contracts; the extra diffusions may both be performed before CCD channel stop-transistor base diffusion, or the n.sup.+ base contact diffusion may be performed thereafter.