Abstract: A programmable interrupt delay in a communication circuit enables accurate timing of an interrupt delay without tying up processor CPU cycles in the execution of a delay loop. The interrupt delay comprises a memory containing the program delay value. A communication circuit which generates an interrupt output corresponding to the transmission of a communication data stream is coupled to a timing circuit having a time value. This timing circuit also has a timing start input, which triggers timing of the timing value upon receipt of the interrupt output. A comparator coupled to the memory and to the timing circuit compares the time value to the delay value and generates a delayed interrupt when the time value and the delay value are equal.

Abstract: A system and method for changing an arbitration priority of a bus master are described. A changing system condition can be detected and used to signal the arbiter to change the priority of one or more bus masters. Timers can be provided to delay the request of a changed priority and to return a bus master to its default priority.