Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Abstract: A method of programming a memory device including a one-time programmable (OTP) cell array configured to include at least one of a protected area and a programmable area are disclosed. The method includes receiving a fuse-program command to initiate a fuse-programming operation; checking whether the programmable area exists in the OTP cell array, terminating the fuse-programming operation when the OTP cell array does not include the programmable area, performing a fuse-programming operation on the programmable area when the OTP cell array includes the programmable area thereby programming fuses to create a fuse-programmed area; setting the fuse-programmed area of the OTP cell array as the protected area.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.

Abstract: A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank. In one arrangement, the controller controls the refresh operation to be selectively performed for a first rank in each of the memory chips during the non-overlapping time periods independently from a refresh operation performed for a second rank in each memory chip. Delay circuits or other logic may be included to ensure that the refresh operations do not overlap.

Abstract: A volatile memory device includes a memory cell array including a plurality of pages and a refresh control circuit. The refresh control circuit may adjust a refresh interval according to a refresh information signal and refreshes the plurality of pages according to the adjusted refresh interval while refreshing weak pages of the plurality of pages at least twice during a refresh period. Each of the weak pages may include at least a weak cell whose data retention time is shorter than a data retention time of normal cells, and the refresh information signal is based on a number of the weak pages. A memory controller and may generate auto refresh commands for volatile memory device(s) based on refresh information reflecting a number of weak pages of the volatile memory device(s). Systems and methods are also disclosed.

Abstract: A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract: In one embodiment, the stacked memory includes a first group of stacked memory chips, a second group of stacked memory chips, and connection terminals configured to electrically connect a first memory chip among the stacked memory chips in the first group to a second memory chip among the stacked memory chips in the second group.

Abstract: A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

Abstract: Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.

Abstract: Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.

Abstract: A multi-port memory device includes first and second ports, a first dedicated memory area assigned to the first port, a plurality of shared memory units having shared access by the first and second ports, a first set of I/O lines for the first dedicated memory area, and a second set of I/O lines for the shared memory units with the second set having more I/O lines than the first set. For example, the second set has N times more I/O lines than the first set, with N being a number of ports of the multi-port memory device or with N being a number of shared memory banks in a shared memory area.

Abstract: A semiconductor device includes a semiconductor substrate; bumps disposed in a plurality of rows along a first axis direction of the semiconductor substrate; and test pads disposed in one or more columns along a second axis direction perpendicular to the first axis direction. The bumps and the test pads form a cross shape in the center portion of the semiconductor substrate. Disposing bumps in the central portion of the semiconductor substrate facilitates forming physical connections between stacked semiconductor devices of a semiconductor stack, regardless of the chip sizes.

Abstract: A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

Abstract: A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.

Abstract: A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.

Abstract: A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

Abstract: In one embodiment, the stacked memory includes a first group of stacked memory chips, a second group of stacked memory chips, and connection terminals configured to electrically connect a first memory chip among the stacked memory chips in the first group to a second memory chip among the stacked memory chips in the second group.