Patents by Inventor Chi-Ta Wu

Chi-Ta Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Giga interposer integration through Chip-On-Wafer-On-Substrate
    Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Neural network engine with tile-based execution
    Patent number: 11436483
    Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: September 6, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Ting Kuo, Chien-Hung Lin, Shao-Yu Wang, ShengJe Hung, Meng-Hsuan Cheng, Chi-Ta Wu, Henrry Andrian, Yi-Siou Chen, Tai-Lung Chen
  • NEURAL NETWORK ENGINE WITH TILE-BASED EXECUTION
    Publication number: 20190220742
    Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 18, 2019
    Inventors: Yu-Ting Kuo, Chien-Hung Lin, Shao-Yu Wang, ShengJe Hung, Meng-Hsuan Cheng, Chi-Ta Wu, Henrry Andrian, Yi-Siou Chen, Tai-Lung Chen