Abstract: The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

Abstract: The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

Abstract: The present invention discloses a current-steering digital-to-analog converter and unit cells. The present invention proposes an n-well bias control circuit for generating a bias voltage whose magnitude is less than the power voltage, therefore the body effect of the transistors could be reduced. Relatively, the threshold voltage and VGS would be reduced. Therefore, even in a low-voltage operation, each transistor could be operated normally in the saturation region. Besides, the plurality of pairs of current switches could be implemented in the same n-well region, instead of being implemented in different n-well regions with leaving a space among each other. Finally, the chip area would be reduced.

Abstract: The present invention discloses an n-well bias preset circuit and method. The present invention electrically connects an n-well bias point of the n-well region to the power at the power-on moment to avoid latch-up effect in the CMOS circuit. After several cycles, the n-well bias point is separated from the power, and electrically connected to the output of the n-well bias circuit for reducing the body effect of the CMOS circuit.