Abstract: An apparatus includes a first differential transmission line and a second differential transmission line. The second differential transmission line is parallel to the first differential transmission line through an overlap region. The first differential transmission line includes a first line and a second line. The first differential transmission line includes N crossovers along the first differential transmission line through the overlap region at which the first line and the second line switch lanes with each other. N is equal to 1+INT {L/(?/C)}, where L is a length of the overlap region, ? is a wavelength of a differential signal carried by the first or second differential transmission line, C is a constant, and INT {L/(?/C)} is {L/(?/C)} rounded down to the nearest integer.

Abstract: A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.

Abstract: An apparatus includes a first differential transmission line and a second differential transmission line. The second differential transmission line is parallel to the first differential transmission line through an overlap region. The first differential transmission line includes a first line and a second line. The first differential transmission line includes N crossovers along the first differential transmission line through the overlap region at which the first line and the second line switch lanes with each other. N is equal to 1+INT {L/(?/C)}, where L is a length of the overlap region, ? is a wavelength of a differential signal carried by the first or second differential transmission line, C is a constant, and INT {L/(?/C)} is {L/?/C)} rounded down to the nearest integer.

Abstract: A variable inductor is disclosed. In accordance with some embodiments of the present disclosure, a variable inductor may comprise a single-turn conductor comprising a first inductor terminal, a second inductor terminal, a first base portion extending from the first inductor terminal to a first intersection location, a second base portion extending from the second inductor terminal to a second intersection location, and a switched portion extending from the first intersection location to the second intersection location, and a switch comprising a first conductive terminal coupled to the first intersection location and a second conductive terminal coupled to the second intersection location.

Abstract: A variable inductor is disclosed. In accordance with some embodiments of the present disclosure, a variable inductor may comprise a single-turn conductor comprising a first inductor terminal, a second inductor terminal, a first base portion extending from the first inductor terminal to a first intersection location, a second base portion extending from the second inductor terminal to a second intersection location, and a switched portion extending from the first intersection location to the second intersection location, and a switch comprising a first conductive terminal coupled to the first intersection location and a second conductive terminal coupled to the second intersection location.

Abstract: A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.

Abstract: A device 20 includes a substrate 22 having an integrated circuit (IC) die 24 coupled thereto. A bond wire 28 interconnects a die bond pad 32 on the IC die 24 with an insulated bond pad 36. Another bond wire 38 interconnects a die bond pad 42 on the IC die 24 with another insulated bond pad 46. The bond wires 28 and 38 serve as radiating elements of a dipole antenna structure 64. A reflector 72 and director 74 can be located on the substrate 22 and/or the IC die 24 to reflect and/or direct a radiation pattern 66 emitted by or received by the antenna structure 64. A trace 82 can be interconnected between the insulated bond pads 36, 46 to form a folded dipole antenna structure 84.

Abstract: A device 20 includes a substrate 22 having an integrated circuit (IC) die 24 coupled thereto. A bond wire 28 interconnects a die bond pad 32 on the IC die 24 with an insulated bond pad 36. Another bond wire 38 interconnects a die bond pad 42 on the IC die 24 with another insulated bond pad 46. The bond wires 28 and 38 serve as radiating elements of a dipole antenna structure 64. A reflector 72 and director 74 can be located on the substrate 22 and/or the IC die 24 to reflect and/or direct a radiation pattern 66 emitted by or received by the antenna structure 64. A trace 82 can be interconnected between the insulated bond pads 36, 46 to form a folded dipole antenna structure 84.

Abstract: Disclosed herein are various high-impedance surfaces having high capacitance and inductance properties and methods for their manufacture. One exemplary high-impedance surface includes a plurality of conductive structures arranged in a lattice, wherein at least a subset of the conductive structures include a plurality of conductive plates arranged along a conductive post so that the conductive plates of one conductive structure interleave with one or more conductive plates of one or more adjacent conductive structure. Another exemplary high-impedance surface includes a plurality of conductive structures arranged in a lattice, where the conductive structures include one or more fractalized conductive plates having either indentions and/or projections that are coextensive with corresponding projections or indentations, respectively, of one or more adjacent conductive structures. Also disclosed are various exemplary implementations of such high-impedance surfaces.

Abstract: Disclosed herein are various high-impedance surfaces having high capacitance and inductance properties. One exemplary high-impedance surface includes a plurality of conductive structures arranged in a lattice, wherein at least a subset of the conductive structures include a plurality of conductive plates arranged along a conductive post so that the conductive plates of one conductive structure interleave with one or more conductive plates of one or more adjacent conductive structure. Another exemplary high-impedance surface includes a plurality of conductive structures arranged in a lattice, where the conductive structures include one or more fractalized conductive plates having either indentions and/or projections that are coextensive with corresponding projections or indentations, respectively, of one or more adjacent conductive structures. Also disclosed are various exemplary implementations of such high-impedance surfaces.

Abstract: An exemplary slot antenna having an antenna cavity that extends over multiple layers is provided. The slot antenna includes a reference conductive layer, a radiating conductive layer having at least one slot opening, one or more intermediate conductive layers disposed between the reference conductive layer and the radiating conductive layer, and two or more dielectric layers. The two or more dielectric layers include at least a first dielectric layer disposed between the reference conductive layer and the one or more intermediate conductive layers and a second dielectric layer disposed between the one or more intermediate conductive layers and the radiating conductive layer. Each of the one or more intermediate conductive layers includes at least one opening substantially devoid of conductive material. Due to its reduced footprint in the x-y plane, the multilayer slot antenna may be embedded in an integrated circuit package for use in a wireless device.

Abstract: An exemplary slot antenna having an antenna cavity that extends over multiple layers is provided. The slot antenna includes a reference conductive layer, a radiating conductive layer having at least one slot opening, one or more intermediate conductive layers disposed between the reference conductive layer and the radiating conductive layer, and two or more dielectric layers. The two or more dielectric layers include at least a first dielectric layer disposed between the reference conductive layer and the one or more intermediate conductive layers and a second dielectric layer disposed between the one or more intermediate conductive layers and the radiating conductive layer. Each of the one or more intermediate conductive layers includes at least one opening substantially devoid of conductive material. Due to its reduced footprint in the x-y plane, the multilayer slot antenna may be embedded in an integrated circuit package for use in a wireless device.

Abstract: A method for automated artwork building which comprises determining a desired die pad pitch, assigning inner lead bonding positions for each lead based on the average die pitch. The desired outer lead bonding position is then determined for each lead. The allowable range of fan in and fan out angles for each lead is computed according to design and manufacturing constraints. An electrical cost function is formulated based on signal lead crosstalk and ground lead simultaneous switching noise. Each lead is then routed. The routing is repeated for each lead for each allowable combination of fan in and fan out angles. Finally the optimal routing is selected based on electrical characteristics.

Abstract: A package (10, 37, 39) capable of spreading heat from a semiconductor die (25). The package (10, 37) includes a heat spreader (11) having a thickness of approximately 0.2 millimeters and a plurality of heat spreader clearance holes (16). The heat spreader (11) is coated with an adhesive material (17) which fills the plurality of heat spreader clearance holes (16). A substrate layer (18) is formed on the adhesive material (17). The substrate layer (18) has conductive traces (20, 24) and conductive pads (21) disposed thereon. A cavity (23) may be present in the package (10, 37, 39) which exposes a portion of the heat spreader (11) and is adapted to receive the semiconductor die (25). The cavity (23) is covered by a cavity sealing means (30, 38).

Abstract: A plurality of conductors (10, 11, 12, 15) are formed into sections (13, 14, 16, 17, 18, 19) having uniform cross-sectional area. Per unit electrical parameters are developed for each section (13, 14, 16, 17, 18, 19). A conductor of the plurality of conductors (10, 11, 12, 15) is partitioned into a number of equal length segments. All other conductors are partitioned into the same number of segments. For each segment, a lumped element model (24, 26, 28, 29) is developed. The model (24, 26, 28, 29) includes a capacitor (33), an inductor (32), a plurality of mutual inductors (36, 38, 31), and a plurality of mutual capacitors (37, 39, 40). Each model (24, 26, 28, 29) of a conductor (10, 11, 12, 15) is serially connected to provide an equivalent circuit (23, 27) of each conductor (10, 11, 12, 15). The circuits (23, 27) are simulated to determine the amount of signal coupling. The conductors (10, 11, 12, 15) are then modified to limit the signal coupling to desired values, and the procedure is repeated.

Abstract: A conventional pin grid array package is provided with microwave frequency signal lines by wire bonding two adjacent conductive lines together. The wire bonding process is done at the same time that a semiconductor device is electrically connected to the pin grid array package. The two adjacent wire bonded conductive lines will have very low reflection or signal loss and therefore can be used with signals having a fast rise time or fast edge rates. The wire bond connection does not significantly degrade a constant impedance line for the signal.