Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

Abstract: A stylus sensing circuit includes a receiving circuit, a demodulation circuit and a detection circuit. The receiving circuit receives a downlink signal from a stylus, wherein the downlink signal includes a plurality of frequency signals. The demodulation circuit, coupled to the receiving circuit, demodulates the downlink signal to extract each of the plurality of frequency signals. The detection circuit, coupled to the demodulation circuit, chooses one of the plurality of frequency signals to perform a signal processing.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

Abstract: A semiconductor device including an active region, a gate dielectric layer, a gate electrode, and a source/drain region is provided. The active region is formed in a substrate. The gate dielectric layer is located on the active region and has an extension area on opposite sides of the gate dielectric layer respectively. The gate electrode is located on the gate dielectric layer and exposes the two extension areas. The source/drain region is located in the active region on one side of the gate dielectric layer.

Abstract: A stylus sensing circuit includes a receiving circuit, a demodulation circuit and a detection circuit. The receiving circuit receives a downlink signal from a stylus, wherein the downlink signal includes a plurality of frequency signals. The demodulation circuit, coupled to the receiving circuit, demodulates the downlink signal to extract each of the plurality of frequency signals. The detection circuit, coupled to the demodulation circuit, chooses one of the plurality of frequency signals to perform a signal processing.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first capacitor conductor disposed over an isolation structure arranged within a substrate. The isolation structure laterally extends past opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is arranged along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is arranged along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps parts of both the capacitor dielectric and the first capacitor conductor.

Abstract: A gate oxide layer for a high voltage transistor is formed using methods that avoid thinning in the corners of the gate oxide layer. A recess is formed in a silicon substrate. The exposed surfaces of the recess are thermally oxidized to form a thermal oxide layer of the gate oxide layer. A high temperature oxide layer of the gate oxide layer is then formed within the exposed surfaces of the recess by chemical vapor deposition. The combination of the thermal oxide layer and the high temperature oxide layer results in a gate oxide layer that does not exhibit the double hump phenomenon in the drain current vs. gate voltage curve. The high temperature oxide layer may include a rim that extends out of the recess.

Abstract: Some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. The integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a perimeter portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.

Abstract: A radio frequency (RF) front-end system and a method for reducing interference are provided. The RF front-end system includes a processing circuit, a first transceiver, an RF front-end circuit, and a first antenna. The RF front-end circuit includes a first switch circuit, a first filter circuit, and a second switch circuit. The first switch circuit and the second switch circuit respectively include first signal paths and second signal paths. The first filter circuit includes an all-pass circuit corresponding to a first frequency band and a first channel filter corresponding to a first frequency channel. The processing circuit executes an anti-interference process, including: switching to the all-pass circuit; executing a channel sounding process to determine usage statuses of a plurality of channels; executing an automatic channel selection process to select a target channel; and switching to the target channel, and controlling the first transceiver to perform signal transmission.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

Abstract: A radio frequency (RF) front-end system and a method for reducing interference are provided. The RF front-end system includes a processing circuit, a first transceiver, an RF front-end circuit, and a first antenna. The RF front-end circuit includes a first switch circuit, a first filter circuit, and a second switch circuit. The first switch circuit and the second switch circuit respectively include first signal paths and second signal paths. The first filter circuit includes an all-pass circuit corresponding to a first frequency band and a first channel filter corresponding to a first frequency channel. The processing circuit executes an anti-interference process, including: switching to the all-pass circuit; executing a channel sounding process to determine usage statuses of a plurality of channels; executing an automatic channel selection process to select a target channel; and switching to the target channel, and controlling the first transceiver to perform signal transmission.

Abstract: An electronic device includes a substrate, at least one electronic element and a heat dissipating electromagnetic shielding structure. The heat dissipating electromagnetic shielding structure is disposed on the substrate and covers the at least one electronic element, wherein the heat dissipating electromagnetic shielding structure includes a shielding frame and a heatsink. The shielding frame includes a plurality of spring members. The spring members are bent toward the substrate and partially abut against the heatsink. When the heatsink and the shielding frame are correspondingly arranged, a shielding space is defined, the electronic element is disposed in the shielding space, and a heat generated by the at least one electronic element is conducted out of the shielding space via the heatsink.

Abstract: An electronic device includes a substrate, at least one electronic element and a heat dissipating electromagnetic shielding structure. The heat dissipating electromagnetic shielding structure is disposed on the substrate and covers the at least one electronic element, wherein the heat dissipating electromagnetic shielding structure includes a shielding frame and a heatsink. The shielding frame includes a plurality of spring members. The spring members are bent toward the substrate and partially abut against the heatsink. When the heatsink and the shielding frame are correspondingly arranged, a shielding space is defined, the electronic element is disposed in the shielding space, and a heat generated by the at least one electronic element is conducted out of the shielding space via the heatsink.

Abstract: A plug-and-play device is provided. The plug-and-play device includes a device housing, a circuit board, a joint and an electromagnetic shielding frame. The circuit board is disposed in the device housing, including a substrate and a plurality of transmission pins, wherein the transmission pins are formed on the substrate. The transmission pins are connected to the joint. The electromagnetic shielding frame covers the transmission pins.

Abstract: A touch structure is provided. The touch structure includes a first sensing electrode, a second sensing electrode, a first dummy pattern and a second dummy pattern. The first sensing electrode and the second sensing electrode are arranged in a staggered manner and electrically insulated from each other. The first dummy pattern is adjacent to the first sensing electrode and has a first pattern acute angle. The second dummy pattern is adjacent to the second sensing electrode and has a second pattern acute angle. The first dummy pattern and the second dummy pattern are separated from each other. The first pattern acute angle and the second pattern acute angle are faced toward the same overlapped portion between the first sensing electrode and the second sensing electrode substantially.

Abstract: An optical touch module and a data loading method thereof are provided. The optical touch module includes a first system-on-chip (SoC), a second SoC and a storage element. The first and the second SoCs are electrically connected to each other and disposed around a touch region of a substrate. The first and the second SoCs each include an image sensor for sensing an image of the touch region. The storage element is electrically connected to the first SoC. The first SoC reads first data and second data stored in the storage element and transmits the second data to the second SoC. The first and the second SoCs respectively process the image of the touch region according to the first data and the second data.