Patents by Inventor Chi-Ting Chen

Chi-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152566
    Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 19, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
  • Patent number: 11145746
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co.y, Ltd.
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Chi On Chui
  • Patent number: 11139384
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Publication number: 20210303817
    Abstract: A method for performing fingerprint sensing is introduced. The method includes performing a predetermined number of consecutive fingerprint sensing cycles; informing a processing unit that a fingerprint sensing driver is ready for providing pre-scanned fingerprint data after each cycle of a fingerprint sensing cycle set, wherein the fingerprint sensing cycle set includes at least one of the fingerprint sensing cycles except for a last one of the fingerprint sensing cycles; and providing the processing unit with the pre-scanned fingerprint data obtained from the each cycle of the fingerprint sensing cycle set. An electronic module capable of performing fingerprint sensing and a computing apparatus capable of performing the same are also provided.
    Type: Application
    Filed: December 3, 2020
    Publication date: September 30, 2021
    Inventors: PING LIU, CHI-TING CHEN
  • Publication number: 20210296112
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Publication number: 20210296182
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210296183
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210287934
    Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Chi-Ching Liu, Yu-Ting Chen, Chang-Tsung Pai, Shun-Li Lan, Yen-De Lee, Chih-Jung Ni
  • Patent number: 11121254
    Abstract: A transistor with strained superlattices as source/drain regions includes a substrate. A gate structure is disposed on the substrate. Two superlattices are respectively disposed at two sides of the gate structure and embedded in the substrate. The superlattices are strained. Each of the superlattices is formed by a repeated alternating stacked structure including a first epitaxial silicon germanium and a second epitaxial silicon germanium. The superlattices serve as source/drain regions of the transistor.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Bo-Shiun Chen, Chun-Jen Chen, Chung-Ting Huang, Chi-Hsuan Tang, Jhong-Yi Huang, Guan-Ying Wu
  • Patent number: 11113376
    Abstract: The present invention discloses a method of finger touch authentication through a fingerprint sensor. The method includes obtaining a plurality of touch operations through the fingerprint sensor, detecting a pattern of the plurality of touch operations; comparing the pattern with a registered pattern to generate a comparison result, and authenticating the plurality of touch operations on the basis of the comparison result, wherein the pattern indicates at least one feature, and the fingerprint sensor is capable of authenticating a fingerprint of a user after or before the finger touch authentication.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 7, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Sheng-Ruei Hsu, Chi-Ting Chen
  • Publication number: 20210265489
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.
    Type: Application
    Filed: June 19, 2020
    Publication date: August 26, 2021
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Chi On Chui
  • Publication number: 20210265219
    Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20210248342
    Abstract: A readout integrated circuit configured to read out sensing signals from an optical sensing panel is provided. The optical sensing panel includes a sensor array for fingerprint sensing. The readout integrated circuit includes a plurality of input terminals, a first discharging circuit and a control circuit. The plurality of input terminals are configured to be coupled to a plurality of output terminals of the optical sensing panel. The first discharging circuit is coupled to one of the plurality of input terminals. The first discharging circuit is configured to discharge one of the plurality of output terminals of the optical sensing panel by a first current during a readout period. The readout integrated circuit reads out a voltage of the output terminal as a sensing signal. The control circuit is coupled to the first discharging circuit. The control circuit is configured to output at least one control signal to control an operating period of the first discharging circuit.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 12, 2021
    Applicant: Novatek Microelectronics Corp.
    Inventor: Chi-Ting Chen
  • Publication number: 20210250537
    Abstract: A readout integrated circuit configured to read out sensing signals from an optical sensing panel including a sensor array for fingerprint sensing is provided. The readout integrated circuit includes a plurality of input terminals, a comparator circuit and a control circuit. The plurality of input terminals are configured to be coupled to a plurality of output terminals of the optical sensing panel. The comparator circuit is configured to receive an output voltage from an output terminal of the plurality of output terminals of the optical sensing panel and at least one reference voltage, compare the output voltage to the at least one reference voltage and output a comparison result. The control circuit is coupled to the comparator circuit. The control circuit is configured to receive the comparison result and determine a supplementary charge amount to be charged to or discharged from the output terminal according to the comparison result.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 12, 2021
    Applicant: Novatek Microelectronics Corp.
    Inventor: Chi-Ting Chen
  • Publication number: 20210223981
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving data; determining whether the data is compressible; when the data is compressible, writing the data into a first type of the physical erasing units; and when the data is incompressible, writing the data to a second type of the physical erasing units.
    Type: Application
    Filed: February 20, 2020
    Publication date: July 22, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Po-Wen Hsiao, Chi-Ting Chen
  • Patent number: 11062110
    Abstract: A fingerprint detection device comprises a plurality of fingerprint sensing circuits and a processor. The plurality of fingerprint sensing circuits is corresponding to a plurality of sensing zones respectively. The processor is electrically coupled to the fingerprint sensing circuits through a shared transmission bus. The processor is configured to receive information of a touched area of each of the sensing zones, determine a transmission sequence according to the touched area of each of the sensing zones, and control the fingerprint sensing circuits to transmit sensing information of the corresponding sensing zones to the processor through the shared transmission bus according to the transmission sequence.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 13, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Jung-Chen Chung, Chi-Ting Chen
  • Publication number: 20210182527
    Abstract: A fingerprint detection device comprises a plurality of fingerprint sensing circuits and a processor. The plurality of fingerprint sensing circuits is corresponding to a plurality of sensing zones respectively. The processor is electrically coupled to the fingerprint sensing circuits through a shared transmission bus. The processor is configured to receive information of a touched area of each of the sensing zones, determine a transmission sequence according to the touched area of each of the sensing zones, and control the fingerprint sensing circuits to transmit sensing information of the corresponding sensing zones to the processor through the shared transmission bus according to the transmission sequence.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Jung-Chen CHUNG, Chi-Ting CHEN
  • Patent number: 10990782
    Abstract: An operating method of an optical fingerprint capture apparatus includes: by the apparatus upon receipt of a scan command from a host, entering an exposure mode where an image sensor thereof is exposed to light carrying information of a fingerprint; by the apparatus upon complete exposure of the image sensor to the light, entering a sample mode where multiple pieces of pixel data that cooperatively represent an image of the fingerprint are obtained and written to a data buffer thereof; and by the apparatus at a predetermined output time point that is later than a start of the sample mode and earlier than an end of the sample mode, outputting an interrupt request to cause the host to start reading the pieces of pixel data from the data buffer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 27, 2021
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chun-Yen Lin, Ping Liu, Chi-Ting Chen
  • Patent number: 10984216
    Abstract: An optical fingerprint recognition system is disclosed. The optical fingerprint recognition system comprises a processing circuit; and an image sensor comprising a pixel array; wherein in an enrollment operation, the processing circuit is configured to set a first exposure time and control the image sensor to capture a first fingerprint image according to the first exposure time and in a matching operation, the processing circuit is configured to set a second exposure time and control the image sensor to capture a second fingerprint image for the matching operation according to the second exposure time; wherein the first exposure time is longer than the second exposure time.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 20, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Chi-Ting Chen
  • Patent number: 10970512
    Abstract: A fingerprint sensing apparatus having a large-area sensing mechanism is provided that includes at least three optical fingerprint sensing circuits and a processing circuit. The at least three optical fingerprint sensing circuits are configured to perform sensing within a plurality of sensing areas to obtain a plurality of sensed images, wherein each of the sensing areas corresponds to one of the optical fingerprint sensing circuits. The processing circuit is electrically coupled to the optical fingerprint sensing circuits to receive the sensed images and is configured to splice the sensed images together to form an integrated sensed image.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 6, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Jung-Chen Chung, Chi-Ting Chen