Patents by Inventor Chi-Ting Huang

Chi-Ting Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12104109
    Abstract: A liquid-crystal (LC) material having negative dielectric anisotropy and the use thereof for optical, electro-optical and electronic purposes, such as for example in LC displays, in particular energy saving displays based on the ECB, IPS or FFS effect, where the liquid crystal medium contains one or more compounds of formula I and one or more compounds compounds of formulae IIA, IIB, IIC and IID
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: October 1, 2024
    Assignee: MERCK PATENT GMBH
    Inventors: Chi-Shun Huang, Sven Christian Laut, Hee-Kyu Lee, Minghui Yang, Harald Hirschmann, Kuang-Ting Chou, Shih-Chieh Hung, Alexander Hahn, Philipp Wucher
  • Patent number: 12102849
    Abstract: A helmet includes a helmet body and a gas detection and purification device. The gas detection and purification device in includes a body, a purification module, a gas-guiding unit, a gas detection module, and a power module. The gas detection module calculates the gas detection data obtained by the gas detection module so as to control the gas-guiding unit to start or stop operation based on the gas detection data. When the gas-guiding unit is in operation, the gas-guiding unit guides the gas into the body and to pass through the purification module for being filtered and purified to become a purified gas, and the gas-guiding unit discharges the purified gas out of the body to the nose portion, or the mouth portion, or both the nose portion and the mouth portion of the wearer for providing the wearer with the purified gas to breath.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 1, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chin-Wen Hsieh, Tsung-I Lin, Yang Ku, Yi-Ting Lu
  • Publication number: 20240312557
    Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.
    Type: Application
    Filed: February 16, 2024
    Publication date: September 19, 2024
    Applicant: MEDIATEK INC.
    Inventors: Che-Wei Chou, Ya-Ting Yang, Shu-Lin Lai, Chi-Kai Hsieh, Yi-Ping Kuo, Chi-Hao Hong, Jia-Jing Chen, Yi-Te Chiu, Jiann-Tseng Huang
  • Publication number: 20240304705
    Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Publication number: 20240304496
    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Inventors: Chung-Ting Ko, Tai-Chun Huang, Jr-Hung Li, Tze-Liang Lee, Chi On Chui
  • Publication number: 20240297163
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: May 12, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20240274715
    Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.
    Type: Application
    Filed: March 21, 2023
    Publication date: August 15, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Hsiang Wang, Yi-Fan Li, Chung-Ting Huang, Chi-Hsuan Tang, Chun-Jen Chen, Ti-Bin Chen, Chih-Chiang Wu
  • Publication number: 20240260260
    Abstract: A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.
    Type: Application
    Filed: March 20, 2023
    Publication date: August 1, 2024
    Inventors: YU TING HUANG, CHI PEI WU
  • Patent number: 12052815
    Abstract: Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 30, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Chih-Chiang Lu, Heng-Ming Nien, Ching-Sheng Chen, Ching Chang, Ming-Ting Chang, Chi-Min Chang, Shao-Chien Lee, Jun-Rui Huang, Shih-Lian Cheng
  • Publication number: 20240241344
    Abstract: An imaging lens including a first lens group, a second lens group, and an aperture stop disposed between the first lens group and the second lens group is provided. The first lens group includes at least one and at most three lenses with refractive powers, and the second lens group has a positive refractive power and includes at least two and at most three lenses with a refractive powers. The imaging lens satisfies conditions of 2 mm<LT<20 mm and 0.8<D1/LT<1.4, where D1 is a lens diameter of the lens closest to the object side, and LT is distance along the optical axis between two outermost lens surfaces at opposite ends of the first lens group and the second lens group.
    Type: Application
    Filed: April 4, 2023
    Publication date: July 18, 2024
    Inventors: HAN-TING HUANG, CHI-YU BAI, CHING-LUNG LAI
  • Publication number: 20230132846
    Abstract: An electronic device is provided, and the manufacturing method of which is to stack a carrier structure on a circuit board having a reflector via a plurality of conductive elements, dispose a micro strip and an antenna layer communicatively connected to the reflector respectively on opposite sides of the carrier structure, dispose an antenna spacer on the carrier structure, cover the antenna spacer with an encapsulation layer, and form an antenna portion communicatively connected to the antenna layer on the encapsulation layer. Therefore, a better antenna performance can be obtained by disposing the micro strip on the bottom layer of the carrier structure and disposing the antenna layer on the top layer of the carrier structure.
    Type: Application
    Filed: November 3, 2022
    Publication date: May 4, 2023
    Inventors: Ying-Chieh PAN, Hsiang-Hua LU, Chi-Ting HUANG
  • Patent number: 11581260
    Abstract: A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 14, 2023
    Assignee: Kore Semiconductor Co., Ltd.
    Inventors: Chi-Ting Huang, Ching-Yu Ni, Hsiang-Hua Lu, Ying-Chieh Pan
  • Publication number: 20220122917
    Abstract: A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.
    Type: Application
    Filed: November 13, 2020
    Publication date: April 21, 2022
    Inventors: CHI-TING HUANG, CHING-YU NI, HSIANG-HUA LU, YING-CHIEH PAN
  • Patent number: 9330215
    Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Hsien Tsai, Chi-Ting Huang, Cheng-Hung Yeh, Hsien-Hsin Sean Lee
  • Publication number: 20150269303
    Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: Taiwan Semiconcuctor Manufacturing Co., Ltd.
    Inventors: Yao-Hsien TSAI, Chi-Ting HUANG, Cheng-Hung YEH, Hsien-Hsin Sean LEE
  • Patent number: 9104835
    Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yang Yeh, Cheng-Hung Yeh, Chi-Ting Huang
  • Publication number: 20150154343
    Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 4, 2015
    Inventors: Chao-Yang YEH, Cheng-Hung YEH, Chi-Ting HUANG
  • Patent number: 8910101
    Abstract: A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manfacturing Co., Ltd.
    Inventors: Chao-Yang Yeh, Cheng-Hung Yeh, Chi-Ting Huang
  • Patent number: 8436645
    Abstract: An information generating apparatus and an operation method thereof are provided. The information generating apparatus includes a first logic contact, a second logic contact, an information output contact and a plurality of switches SW(i,j), wherein SW(i,j) represents a jth switch in an ith layer, 1?i?L, and 1?j?2(i?1). The switch SW(i,j) has a first input terminal, a second input terminal and an output terminal, wherein the output terminal is selectively connected to the first or the second input terminal. The first and the second input terminals of the switches SW(Lj) in the Lth layer are respectively connected to the first logic contact and the second logic contact. The first and the second input terminals of the switch SW(i,j) in other layers are respectively connected to the output terminals of the switches SW(i+1,2j?1) and SW(i+1,2j). The output terminal of the switch SW(1,1) is connected to the information output contact.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: May 7, 2013
    Assignee: Himax Technologies Limited
    Inventors: Chi-Ting Huang, Chia-Chinq Chu
  • Publication number: 20120306560
    Abstract: An information generating apparatus and an operation method thereof are provided. The information generating apparatus includes a first logic contact, a second logic contact, an information output contact and a plurality of switches SW(i,j), wherein SW(i,j) represents a jth switch in an ith layer, 1?i?L, and 1?j?2(i?1). The switch SW(i,j) has a first input terminal, a second input terminal and an output terminal, wherein the output terminal is selectively connected to the first or the second input terminal. The first and the second input terminals of the switches SW(Lj) in the Lth layer are respectively connected to the first logic contact and the second logic contact. The first and the second input terminals of the switch SW(i,j) in other layers are respectively connected to the output terminals of the switches SW(i+1,2j-1) and SW(i+1,2j). The output terminal of the switch SW(1,1) is connected to the information output contact.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 6, 2012
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chi-Ting Huang, Chia-Chinq Chu