Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.

Abstract: An auxiliary operation device for a droplet dispenser includes a droplet sensor, an imaging device and a processor. The droplet sensor has a detected area located between a droplet dispenser and a target area, wherein the droplet sensor detects a droplet output from the droplet dispenser, and outputs a corresponding droplet detection signal. The imaging device captures an image of the target area. The processor obtains a dripping time point at which the droplet passes through the detected area according to the droplet detection signal, and determines whether the target area is shielded within a first time range according to the image, so as to evaluate whether the droplet has successfully dropped into the target area. The above-mentioned auxiliary operating device of the droplet dispenser can objectively determine whether the droplets successfully drops into the target area, and improve the accuracy of judgment.

Abstract: The present invention relates to liquid-crystalline (LC) media and to LC displays (LCDs) containing these media, in particular to LCDs of the twisted nematic (TN) mode, preferably to displays of the LCOS (LC on silicon) mode.

Abstract: A gas detection and cleaning system for a vehicle is disclosed and includes an external modular base, a gas detection module and a cleaning device. The gas detection module is connected to a first external connection port of the external modular base to detect a gas in the vehicle and output the information datum. The information datum is transmitted through the first external connection port to a driving and controlling module of the external modular base, processed and converted into an actuation information datum for being externally outputted through a second external connection port of the external modular base. The cleaning device is connected with the second external connection port through an external port to receive the actuation information datum outputted from the second external connection port to actuate or close the cleaning device.

Abstract: An electronic device is provided, and the manufacturing method of which is to stack a carrier structure on a circuit board having a reflector via a plurality of conductive elements, dispose a micro strip and an antenna layer communicatively connected to the reflector respectively on opposite sides of the carrier structure, dispose an antenna spacer on the carrier structure, cover the antenna spacer with an encapsulation layer, and form an antenna portion communicatively connected to the antenna layer on the encapsulation layer. Therefore, a better antenna performance can be obtained by disposing the micro strip on the bottom layer of the carrier structure and disposing the antenna layer on the top layer of the carrier structure.

Abstract: A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.

Abstract: A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.

Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Abstract: A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.

Abstract: An information generating apparatus and an operation method thereof are provided. The information generating apparatus includes a first logic contact, a second logic contact, an information output contact and a plurality of switches SW(i,j), wherein SW(i,j) represents a jth switch in an ith layer, 1?i?L, and 1?j?2(i?1). The switch SW(i,j) has a first input terminal, a second input terminal and an output terminal, wherein the output terminal is selectively connected to the first or the second input terminal. The first and the second input terminals of the switches SW(Lj) in the Lth layer are respectively connected to the first logic contact and the second logic contact. The first and the second input terminals of the switch SW(i,j) in other layers are respectively connected to the output terminals of the switches SW(i+1,2j?1) and SW(i+1,2j). The output terminal of the switch SW(1,1) is connected to the information output contact.

Abstract: An information generating apparatus and an operation method thereof are provided. The information generating apparatus includes a first logic contact, a second logic contact, an information output contact and a plurality of switches SW(i,j), wherein SW(i,j) represents a jth switch in an ith layer, 1?i?L, and 1?j?2(i?1). The switch SW(i,j) has a first input terminal, a second input terminal and an output terminal, wherein the output terminal is selectively connected to the first or the second input terminal. The first and the second input terminals of the switches SW(Lj) in the Lth layer are respectively connected to the first logic contact and the second logic contact. The first and the second input terminals of the switch SW(i,j) in other layers are respectively connected to the output terminals of the switches SW(i+1,2j-1) and SW(i+1,2j). The output terminal of the switch SW(1,1) is connected to the information output contact.

Abstract: A flat panel display includes a scaler, a first transmitter, a second transmitter, a first receiver, a second receiver, a compensated driving unit, a timing controller, a data driver, a scan driver and a panel. The scaler generates first and second adjusted image data according to an image signal, and outputs the first and second adjusted image data to the first and second receivers through the first and second transmitters, respectively. The compensated driving unit outputs compensated driving data according to the first and second adjusted image data. The timing controller receives the compensated driving data, and outputs the compensated driving data to the data driver and a scan-starting signal to the scan driver according to timing so as to control each row of pixels on the panel sequentially. The data driver receives the compensated driving data and then outputs a driving voltage to each row of pixels.

Abstract: In a liquid crystal display or panel and a method of driving the same, in response to the receipt of a plurality of image control signals each intended for one of the data lines, the image control signals are modified in accordance with different characteristics of the data lines. The modified image control signals are outputted to the respective data lines to drive the liquid crystal display or panel.

Abstract: A method of operating a display includes deriving first pixel data for overdriving pixel circuits of the display from initial gray levels to target gray levels based on values in the first and second lookup tables, rendering the second lookup table unavailable in memory in response to a change in a temperature of the display, and deriving second pixel data using the first lookup table for overdriving the pixel circuits when the second lookup table is unavailable in the memory.

Abstract: An embodiment of the invention provides a timing controller. The timing controller comprises a frequency detector, a signal generator and a multiplexer. The frequency detector receives a reference clock signal and an input clock signal to generate a decision signal. The signal generator generates a first signal and a second signal. The multiplexer receives and outputs one of the first signal and the second signal according to the decision signal.

Abstract: A method of operating a display includes deriving first pixel data for overdriving pixel circuits of the display from initial gray levels to target gray levels based on values in the first and second lookup tables, rendering the second lookup table unavailable in memory in response to a change in a temperature of the display, and deriving second pixel data using the first lookup table for overdriving the pixel circuits when the second lookup table is unavailable in the memory.