Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

Abstract: A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Abstract: An electronic device is provided, and the manufacturing method of which is to stack a carrier structure on a circuit board having a reflector via a plurality of conductive elements, dispose a micro strip and an antenna layer communicatively connected to the reflector respectively on opposite sides of the carrier structure, dispose an antenna spacer on the carrier structure, cover the antenna spacer with an encapsulation layer, and form an antenna portion communicatively connected to the antenna layer on the encapsulation layer. Therefore, a better antenna performance can be obtained by disposing the micro strip on the bottom layer of the carrier structure and disposing the antenna layer on the top layer of the carrier structure.

Abstract: A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.

Abstract: A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.

Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

Abstract: A method for verifying the design of an IC having a plurality of tiers includes conducting a layout versus schematic (“LVS”) check to separate a plurality of devices of a plurality of design layouts, wherein each design layout corresponds to a respectively different tier having the respective devices. A plurality of adjacent tier connections are generated between one of the devices in respectively different tiers from each other, using a computing device. A first RC extraction for each of the tiers is performed to compute couplings between each of the plurality of devices of the corresponding design layout. A second RC extraction for each of the adjacent tier connections is performed.

Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Abstract: A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.

Abstract: An information generating apparatus and an operation method thereof are provided. The information generating apparatus includes a first logic contact, a second logic contact, an information output contact and a plurality of switches SW(i,j), wherein SW(i,j) represents a jth switch in an ith layer, 1?i?L, and 1?j?2(i?1). The switch SW(i,j) has a first input terminal, a second input terminal and an output terminal, wherein the output terminal is selectively connected to the first or the second input terminal. The first and the second input terminals of the switches SW(Lj) in the Lth layer are respectively connected to the first logic contact and the second logic contact. The first and the second input terminals of the switch SW(i,j) in other layers are respectively connected to the output terminals of the switches SW(i+1,2j?1) and SW(i+1,2j). The output terminal of the switch SW(1,1) is connected to the information output contact.

Abstract: An information generating apparatus and an operation method thereof are provided. The information generating apparatus includes a first logic contact, a second logic contact, an information output contact and a plurality of switches SW(i,j), wherein SW(i,j) represents a jth switch in an ith layer, 1?i?L, and 1?j?2(i?1). The switch SW(i,j) has a first input terminal, a second input terminal and an output terminal, wherein the output terminal is selectively connected to the first or the second input terminal. The first and the second input terminals of the switches SW(Lj) in the Lth layer are respectively connected to the first logic contact and the second logic contact. The first and the second input terminals of the switch SW(i,j) in other layers are respectively connected to the output terminals of the switches SW(i+1,2j-1) and SW(i+1,2j). The output terminal of the switch SW(1,1) is connected to the information output contact.

Abstract: A flat panel display includes a scaler, a first transmitter, a second transmitter, a first receiver, a second receiver, a compensated driving unit, a timing controller, a data driver, a scan driver and a panel. The scaler generates first and second adjusted image data according to an image signal, and outputs the first and second adjusted image data to the first and second receivers through the first and second transmitters, respectively. The compensated driving unit outputs compensated driving data according to the first and second adjusted image data. The timing controller receives the compensated driving data, and outputs the compensated driving data to the data driver and a scan-starting signal to the scan driver according to timing so as to control each row of pixels on the panel sequentially. The data driver receives the compensated driving data and then outputs a driving voltage to each row of pixels.

Abstract: In a liquid crystal display or panel and a method of driving the same, in response to the receipt of a plurality of image control signals each intended for one of the data lines, the image control signals are modified in accordance with different characteristics of the data lines. The modified image control signals are outputted to the respective data lines to drive the liquid crystal display or panel.

Abstract: A method of operating a display includes deriving first pixel data for overdriving pixel circuits of the display from initial gray levels to target gray levels based on values in the first and second lookup tables, rendering the second lookup table unavailable in memory in response to a change in a temperature of the display, and deriving second pixel data using the first lookup table for overdriving the pixel circuits when the second lookup table is unavailable in the memory.

Abstract: An embodiment of the invention provides a timing controller. The timing controller comprises a frequency detector, a signal generator and a multiplexer. The frequency detector receives a reference clock signal and an input clock signal to generate a decision signal. The signal generator generates a first signal and a second signal. The multiplexer receives and outputs one of the first signal and the second signal according to the decision signal.

Abstract: A method of operating a display includes deriving first pixel data for overdriving pixel circuits of the display from initial gray levels to target gray levels based on values in the first and second lookup tables, rendering the second lookup table unavailable in memory in response to a change in a temperature of the display, and deriving second pixel data using the first lookup table for overdriving the pixel circuits when the second lookup table is unavailable in the memory.

Abstract: In a liquid crystal display or panel and a method of driving the same, in response to the receipt of a plurality of image control signals each intended for one of the data lines, the image control signals are modified in accordance with different characteristics of the data lines. The modified image control signals are outputted to the respective data lines to drive the liquid crystal display or panel.

Abstract: A computer system includes a nonvolatile memory for storing instructions, a microprocessor, for controlling operation of the computer system, and a cache system coupled to the microprocessor and directly connected to the nonvolatile memory. The cache system is for providing a requested instruction to the microprocessor. If the requested instruction is cached in the cache system, the cache system sends the requested instruction to the microprocessor; otherwise, the cache system retrieves the requested instruction from the nonvolatile memory, caches the requested instruction, and sends the requested instruction to the microprocessor.