Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.

Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.

Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A lithography method in semiconductor fabrication is provided. The method includes generating a plurality of drops of a target material through a plurality of nozzles, adjacent two of the plurality of nozzles having a distance less than a width of a first one of the adjacent two of the plurality of nozzles, wherein the plurality of drops are aggregated to an elongated droplet; generating a laser pulse to convert the elongated droplet into plasma that generates an extreme ultraviolet (EUV) radiation; exposing a semiconductor substrate to the EUV radiation.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: A target detection method includes generate a frequency modulated continuous wave (FMCW) signal; send the FMCW signal through a radar module; receive a first echo signal and a second echo signal reflected by a target and respectively corresponding to a first output signal and a second output signal; process the first echo signal and the second echo signal to correspondingly obtain a first time domain signal S(t1) and a second time domain signal S(t2); process the first time domain signal S(t1) and the second time domain signal S(t2) to obtain a differential time domain signal ?S(t) which satisfies ?S(t)=S(t2)-S(t1); convert the differential time domain signal ?S(t) into an intermediate frequency (IF) signal through Fast Fourier Transform (FFT); calculate a relative distance or a relative velocity of the target relative to the radar module based on the IF signal.

Abstract: A polyphenylene ether bismaleimide resin is provided. The polyphenylene ether bismaleimide resin (PPE-BMI) is formed from a modified polyphenylene ether diamine and a maleic anhydride by a condensation polymerization. The modified polyphenylene ether diamine is formed by reacting a phenol-based compound with a polyphenylene ether.

Abstract: A server system includes a server host and a server device. The server host includes a first casing and an electrical substrate. The electrical substrate includes a first dock portion, a first metal shell, and a first magnetic piece. The first magnetic piece is in the first metal shell. The server device includes a second casing and a mainboard. The mainboard includes a second dock portion, a second metal shell, and a second magnetic piece. The second magnetic piece is in the second metal shell. The second dock portion is adapted to be docked with the first dock portion. A magnetic attraction force is generated between the first magnetic piece and the first magnetic piece, so that the second dock portion is docked with the first dock portion. Accordingly, the connection between the first dock portion and the second dock portion can be ensured.

Abstract: An apparatus includes an ultrasonic sensor stack, a foldable display stack that includes a display stiffener, and an additional stiffener between the ultrasonic sensor stack and the foldable display stack. The additional stiffener forms an acoustic resonator with the display stiffener and an adhesive layer between the display stiffener and the additional stiffener in order to amplify transmission of ultrasonic waves transmitted by the ultrasonic sensor stack. The additional stiffener includes a material having a high modulus of elasticity, low density, and high acoustic impedance value. In some cases, the additional stiffener includes a metal, a ceramic, a glass, or a glass ceramic. The additional stiffener increases an overall stiffness and mechanical integrity of the apparatus so that a foam backer may be omitted from the ultrasonic sensor stack.

Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are provided herein. The semiconductor device includes a substrate; a fin structure arranged on the substrate and including a ridge portion and a bottom portion between the ridge portion and the substrate, wherein the ridge portion comprises a channel region and a fin region between the channel region and the bottom portion, a critical dimension of the bottom portion in a cross-fin direction is gradually increased toward the substrate to twice or more of a critical dimension of the channel region in the cross-fin direction; a metal gate structure disposed on the fin structure extending the cross-fin direction; and an epitaxy region disposed beside the metal gate structure in a lengthwise direction of the fin structure and connected to the fin structure.

Abstract: A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

Abstract: A structure for enhancing sidewall marking contrast and tire with the same are disclosed. The structure includes a plurality of structural units each having at least three quadrilaterals extending outward radiatively from a center thereof so that the structural unit form a code on a sidewall of a tire. The structure enhances sidewall marking contrast and increase observability of the code against the sidewall, thereby helping impress consumers with accentuated product distinctiveness and/or brand image.

Abstract: Methods for synthesizing a hydrogel having tunable hydrolylic degradation kinetics according to certain embodiments include synthesizing a norborene-functionalized polyethylene glycol macromer having an ester linkage between a polyethylene glycol domain of the macromer and a norbornene domain of the macromer and having a carboxyl group on the norbornene; and reacting a quantity of such macromers with a quantity of dithiol molecules by an ultraviolet-initiated photo-gelation reaction to yield a hydrogel. Such macromers and such hydrogels form additional aspects of the disclosure, as do a wide variety of methods for tuning and for using such hydrogels.

Abstract: A display panel includes a data line and a pixel circuit under test. Pixel circuit under test is coupled to data line, and is configured to receive a first detecting signal from a detecting signal source and receive a second detecting signal from a pixel data signal source. Pixel circuit under test is configured to generate a driving current to read the first detecting signal and the second detecting signal so as to generate a detection result signal. Pixel circuit under test includes a luminous element and a bypass circuit. Luminous element is configured to emit a light according to the driving current. Bypass circuit is coupled to luminous element and data line, and is configured to transmit the detection result signal to detecting signal source through data line according to a test control signal so that detecting signal source determines whether pixel circuit under test is abnormal.

Abstract: The present disclosure provides expression vectors comprising at least two nucleic acid sequences, namely a nucleic acid sequence encoding an anti-HPRT RNAi, and a nucleic acid sequence encoding a gamma globin gene. In some embodiments, the viral vector is a self-inactivating lentiviral vector. In some embodiments, the gamma-globin gene is used to genetically correct sickle cell disease or ?-thalassemia or to reduce symptoms thereof.

Abstract: Disclosed herein are methods of treating or preventing a lung disorder comprising administering to a subject a composition comprising an agent that modulates activity and/or expression of Epithelial Membrane Protein 2 (EMP2) in an amount effective to treat or prevent the lung disorder and compositions useful in such for methods.